Reset Operation for a 16-bit PIC® MCU

Last modified by Microchip on 2023/11/10 11:07

Microchip 16-bit PIC® MCUs and dsPIC® Digital Signal Controllers (DSC) can be reset from seven sources:

  • Power-on Reset (POR)
  • Master Clear Pin Reset (MCLR) (commonly called the reset pin on non-Microchip devices)
  • Software Reset Instruction executed (SWR)
  • Watchdog Timer Reset (WDTR)
  • Brown-out Reset (BOR)
  • Trap Conflict Reset (TRAPR)*
  • Illegal Op-code / Uninitialized W register (IOPUWR)*

Please refer to the "Notes" section on this page.

Simplified Block Diagram Of a Reset

Block Diagram of System Reset

Reset Control Register

16-bit MCUs and DSCs have a Reset Control register (RCON). When a reset occurs, RCON is updated to indicate the source of the reset. In addition to reporting reset conditions, RCON also contains information on the WDT and some power-saving modes. RCON can be examined by an application's start-up code to see why a device entered reset.

RCON: Reset Control Register

RCON Register Bit Definitions

bit 15

TRAPR: Trap Reset Flag bit

1= A Trap Reset has occurred
0= A Trap Reset has not occurred

bit 14

IOPUWR: Illegal Opcode or Uninitialized W register Access bit

1= An Illegal Opcode or Uninitialized W Register used as a Pointer Reset has occurred
0= An Illegal Opcode or Uninitialized W Register Reset has not occurred

bit 7

EXTR: External Reset (MCLR) bit

1= A Master Clear pin Reset has occurred
0= A master Clear pin Reset has not occurred

bit 6

SWR: Software Reset Instruction Flag bit

1= A Software Reset has occurred
0= A Software Reset has not occurred

bit 4

WDTO: Watchdog Timer Time-out bit

1= A Watchdog Timer Time-out has occurred
0= A Watchdog Time-out has not occurred

bit 1

BOR: Brown-out Reset Flag bit

1= A Brownout Reset (or POR) has occurred
0= A Brownout Reset has not occurred

bit 0

POR: Power-on Reset Flag bit

1= A Power-on Reset has occurred
0= A Power-on Reset has not occurred

All of the reset status bits in RCON may be set or cleared in software. Setting one of these bits in software will not cause a device reset.

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Default Interrupt Vector

The MPLAB® XC16 C compiler places an SWR instruction at the Interrupt Vector location for interrupt sources in which the application does not provide their own service routine. If an unexpected or non-maskable interrupt was to occur, the SWR instruction will cause a device reset to occur.

Diagram Showing Interrupt Vectors Populated with SWR as Default by Compiler

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Clock Setting After a Reset

In most instances, the clock setting at reset will be determined by the device's configuration words. For devices with clock switching enabled, the initial clock setting is determined COSC<2:0> in the OSCCON register.

OSCCON: Oscillator Control Register - (High byte)

OSCCON Register High Byte Bit Definitions

OSCCON: Oscillator Control Register - (Low byte)

OSCCON Register Low Byte Bit Definitions


R = Readable Bit
u = Bit is unchanged
'1' = bit is set

W = Writable Bit
x = Bit is unknown
'0' = Bit is cleared

U = Unimplemented Bit, read as '0'
-n/n = Value at POR nad BOR/Value at all other resets
-n = Value at POR reset

bit 14-12

COSC<2:0>: Current Oscillator Selection bits

111 = Fast RC Oscillator with Divide-by-N (FRCDIVN)
110 = Fast RC Oscillator with Divide-by-16 (FRCDIV16)
101 = Low Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (XTPLL,HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with PLL ( FRCPLL)
000 = Fast RC Oscillator (FRC)

The amount of time it takes between entering a reset and executing the first line of code depends upon the oscillator being used. The primary and secondary oscillators must synchronize with an external clock source at reset and can take considerable time to become stable. Internal oscillators have no external dependency and become stable very quickly. Based upon the oscillator selected by the configuration bits, the device will wait a pre-set amount of time, allowing the clock to stabilize before exiting reset. Please consult the datasheet of the device you are using to determine the start-up time for the selected oscillator.

16-bit MCUs and DSC configured for two-speed start-up immediately begin the boot-up process with the internal Fast RC (FRC) Oscillator, switching to the Primary Oscillator when it becomes stable.

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Register Settings at Reset

Most Microchip peripheral Special Function Registers (SFRs) are located in volatile RAM cells and are subject to having their values changed by a reset. Microchip datasheets contain a legend for each SFR detailing the values at reset ( see the following diagram)


  • The lowercase letters u and x and the numbers 1 and 0 indicate the value of each bit after a reset.
  • If an SFR bit has a different value at a POR or BOR reset than it has from other sources, both values will be listed, separated by a slash.

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Memory values at Reset

A POR will result in the loss of all data memory. While resets other than POR may not change the content of memory, applications should not presume the values of the variables have not been changed.

C compilers invoke a pre-defined startup routine before the first user-written instruction is executed. The start-up routine runs after each reset. The purpose of the start-up routine is to prepare the system to run a C program. The typical startup code supplied by a compiler initializes the contents of memory overwriting the post-reset value of all variables.

The MPLAB XC16 compiler offers the Persistent directive, allowing the developer to exclude some variables from start-up initialization. Some compilers provide the option of running the start-up code without initializing variables. Please consult the manual of the compiler you are using to ensure you understand the validity of the variables in your application after a reset occurs.

Program Execution at Reset

The compiler places the application's start-up code at address 0x200. The user's main function is placed beyond the start-up code in program memory. At address 0, the compiler places the assembly command "GOTO address 0x200".

At reset, the Program Counter is loaded with the value of 0 by the hardware causing program execution to begin at address 0. The GOTO @0x200 instruction allows the program counter to by-pass the Interrupt Vector Tables and begin executing the startup code.

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A Trap Conflict Reset (TCR) occurs when a hard and a soft trap occur at the same time.


A device reset is generated if the device attempts to execute an illegal opcode value that was fetched from program memory. If a device reset occurs as a result of an illegal opcode value, the IOPUWR status bit (RCON<14>) is set.

The Illegal Opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the Illegal Opcode Reset, use only the lower 16 bits of each program memory section to store the data values. The upper eight bits should be programmed with 3Fh which is an illegal opcode value.

The W register array (with the exception of W15) is cleared during all resets and is considered uninitialized until written to. An attempt to use an uninitialized register as an Address Pointer causes a device reset and sets the IOPUWR status bit (RCON<14>).

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