16-bit PIC® MCU Architecture

Last modified by Microchip on 2023/11/09 09:03

Harvard Architecture

PIC24 MCUs and dsPIC® Digital Signal Controllers (DSCs) share the same modified Harvard Architecture. An embedded processor using a Harvard architecture has separate data and instructions buses.

Block Diagram of PIC24 Architecture

Simplified Bock Diagram of a PIC24/dsPIC® Digital Signal Controller (DSC)

  • The CPU fetches 24-bit wide instructions from Program Memory over the instruction bus
  • Data Memory and peripherals operations occur on a separate 16-bit data bus.

Separate data and instruction buses provide for a deterministic instruction period through the use of a two-stage pipeline. One instruction is executed on the data bus while the next instruction if fetched on the instruction bus.

Diagram of PIC24 Two-stage Pipeline

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CPU and Instruction Set

The PIC24's CPU has 76 instructions each with several addressing modes. The dsPIC DSC contains the same 76 MCU instructions as the PIC24 but adds 19 DSP specific instructions.

Memory Architecture

Program Memory

PIC24 MCUs and dsPIC DSCs have 24-bit wide Flash memory to store program instructions. Each program memory instruction takes two even word-aligned addresses. The least significant word is assigned the even address. The most significant word is assigned the higher (odd-numbered) address. Only the lower eight bits of the most significant word are implemented. If read, the upper 8-bits of the most significant word will appear as zero.

Diagram of PIC24's 24-bit Program Memory

Program memory is accessed by a 23-bit program counter. When pointing to an instruction, the least significant bit of the program counter will always be zero. While the program counter is capable of addressing up to 4 M instructions, no currently available 16-bit MCU or DSC contains this amount of memory.

Simplified diagram of program memory on PIC24

  • The first 512 bytes of program memory are used for the reset and interrupt vectors.
  • The space for the application program starts at address 0 x 0200.
  • Located at addresses, not accessible by the program counter, are the Device ID and the device's Configuration Registers.

More information on the program memory, including how a program can read and write to on-board Flash, can be found on this site's 16-bit Program Memory page.

Data Memory

PIC24 MCUs and dsPIC DSCs can address 64 kBytes of data memory. The amount of data memory available varies from device to device. Only the lower 32 kBytes can be directly populated with RAM. Under program control, the upper 32 kBytes of address space can either point to a section of program memory or extended data memory.

Simplified diagram of data memory on PIC24

The first 2 kBytes of data memory contains the registers controlling the I/O ports and peripherals.

If a device supports Direct Memory Access (DMA) transfers, a dual-port buffer in memory is located immediately above the installed data RAM. The DMA control peripheral transfers data between this memory buffer and selected peripherals with minimal CPU intervention.

A full description of the data memory, including details of how C compilers use data memory, can be found on the Data memory page.

Accessing Flash Memory from RAM

Program Space Visibility (PSV) is the process that allows the upper 32 kBytes of data memory addresses to point to a block of Flash memory.

Diagram of Program Space Visibility Mapping Flash Memory into RAM Space

Program Space Visibility (PSV) maps select blocks of flash program memory into the upper 32 KB of data memory space to provide quick access to literal constants and Flash-based data tables.

A description of how an application can implement PSV is provided on the PSV page.

Extending Data Memory

Extending the data space to allow access to RAM with the upper 32 kBytes. Byte addresses can be accomplished on 16-bit PIC MCUs and DSCs.

Diagram of Extended Data Space Memory

  • Extended Data Services (EDS) extends the amount of RAM the CPU can access by mapping 32 KB blocks of memory into the upper 32 KB bytes of the data memory space.
  • Only one 32 KB block of EDS memory can be mapped in at a time.
  • The upper portion of data memory space is shared with Program Space Visibility (PSV).
  • Useful for graphics, USB, and communication intense applications.

The Extended Data memory page gives details on using Extended Data Space (EDS) memory.

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Accessing the Peripherals

All peripherals and I/O pins are mapped into memory on 16-bit MCU and DSC families. Modifying a peripheral or accessing an I/O pin is accomplished by reading from or writing to Special Functions Registers (SFRs). The SFRs are located in the first 2 kBytes of data memory space.

Accessing Peripherals Through the Special Function Registers (SFRs)

The 16-bit peripherals page provides explanations and sample code showing how to work with the 16-bit family's peripherals.

Exception Handling (Interrupts and Traps)

Map of Interrupt Vectors in Program Memory Space

16-bit PIC® MCU interrupts have the following characteristics: 

  • Separate interrupt vector for each interrupt source.
  • Preemptive interrupts based upon user selected priority.
  • Run-time control to enable, disable, or change the priority of all interrupts.
  • Alternate vector table to allow all interrupts to be redirected at run-time.
  • Provisions to support identification and processing of non-maskable interrupt (traps).

A comprehensive discussion of the interrupt process as well as example code can be found on the Interrupt Processing page.

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MCU Configuration Registers

Configuration Bits are a collection of binary data located in the Flash program memory of a PIC MCU or dsPIC DSC. Configuration bits are generated by user-written code and become part of the HEX file programmed into the device. Configuration bits are not executable code as they are located at addresses not accessible by the program counter. Configuration bits complete circuitry which enables or disables hardware features of the device.

Configuration bits cannot be modified during run-time.

The Special Features of MCU operation controlled by the configuration bits include:

  1. System Clocking
  2. Power Management
  3. Device Security

Configuration Registers in Memory Map

The MCU Configuration Page provides details of the configuration bits and code examples of how they can be programmed.

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What happens at Reset and Startup?

At start-up, or when a release from Reset occurs, the following happens:

  1. All registers revert to their predefined reset state.
  2. The program counter is cleared which results in executing the instruction at address 0 x 0000.

By default, the MPLAB® XC16 compiler places the start of the user code at address 0 x 0200 and inserts a GOTO 0 x 0200 instruction at address 0 x 0000.

16-bit MCU and DSCs can be reset from several sources. A full explanation of the reset operations, including examples of how to detect anomalous resets, can be found in the 16-bit start-up page.

DSC Enhancements

dsPIC DSCs have the same architecture as a PIC24 but add 19 DSP instructions. Many of these DSP instructions require two operands to be concurrently retrieved from memory. To accommodate the need for dual access of data memory, dsPIC DSCs provide for the data RAM to be split into two regions, each with its own bus.

Diagram of dsPIC Architecture when Executing a DSP Instruction

Simplified Block Diagram of a dsPIC® Digital Signal Controller (DSC) when Executing a Digital Signal Processor (DSP) InstructionCaption

When a dsPIC DSC executes a DSP instruction:

  • Data memory appears to consist of two regions: X and Y.
  • Two data buses are available to concurrently access data memory. One bus accesses the X memory space and the other is dedicated to accessing the Y memory.
  • Simultaneous read/modify/write-backs may be executed on both data buses.

When a dsPIC executes one of the 76 MCU commands, the data memory appears as one contiguous region accessed by a single data bus.

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The DMA controller transfers data between a peripheral's registers and memory. The 16-bit DMA controller uses dual-ported memory and a control scheme which allows transfers to occur with no impact on CPU operation.

Diagram Showing how DMA Accesses Memory Independent of CPU

The DMA controller supports eight independent channels. Each channel can be configured for transfers to or from selected peripherals. Peripherals supported by the DMA controller include:

  • ECAN™ technology
  • 10-bit/12-bit Analog-to-Digital Converter (ADC)
  • Serial Peripheral Interface (SPI)
  • Universal Asynchronous Receiver Transmitter (UART)
  • Input Capture
  • Output Compare

Learn More

16-bit Peripherals
16-bit Software Development
Microchip 32-bit MCUs
Microchip 8-bit PIC MCUs
Microchip 8-bit AVR MCUs

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