This site will be unavailable on Friday 21 February from 11:00AM to 5:00PM MST (1800 to 2400 UTC) for system maintenance.PIC32MX Oscillator - Peripheral Bus Clock (PBCLK)
Last modified by Microchip on 2023/11/10 11:08
Peripheral Bus Clock (PBCLK)
The peripheral clock is derived from the System Clock (SYSCLK) divided by the peripheral clock divisor setting (÷1, ÷2, ÷4, ÷8).
The peripheral bus frequency can be changed on the fly by writing a new value to the divisor bits. These bits are protected from accidental writes with an unlock sequence. A state machine ensures a stable transition from one clock frequency to another.
PBCLK can also be driven out of the CLKO pin.
The default PBCLK divider can be configured at program time and the MPLAB® Harmony functions can be used to configure it at run-time. These functions will perform all unlocking/locking and state machine control for you.
// default PBCLK = SYSCLK/2
#pragma config FPBDIV = DIV_2
...
// PBCLK=SYSCLK/2
PLIB_OSC_PBClockDivisorSet(OSC_ID_0, OSC_PERIPHERAL_BUS_1, 2);
// enable PBCLK
PLIB_OSC_PBOutputClockEnable(OSC_ID_0, OSC_PERIPHERAL_BUS_1);
// disable PBCLK
PLIB_OSC_PBOutputClockDisable(OSC_ID_0, OSC_PERIPHERAL_BUS_1);
#pragma config FPBDIV = DIV_2
...
// PBCLK=SYSCLK/2
PLIB_OSC_PBClockDivisorSet(OSC_ID_0, OSC_PERIPHERAL_BUS_1, 2);
// enable PBCLK
PLIB_OSC_PBOutputClockEnable(OSC_ID_0, OSC_PERIPHERAL_BUS_1);
// disable PBCLK
PLIB_OSC_PBOutputClockDisable(OSC_ID_0, OSC_PERIPHERAL_BUS_1);