PIC32MX Oscillator - System Clock (SYSCLK)
Last modified by Microchip on 2023/11/09 09:01
System Clock (SYSCLK) Generation
The System Clock (SYSCLK) provides the time base for the CPU, peripheral clock, Direct Memory Access (DMA), interrupts, and Flash. SYSCLK is determined from one of the input clocks shown in the diagram: System Phased Lock Loop output (POSC or FRC with PLL), Primary Oscillator, Fast RC oscillator, FRCDIV16, FRCDIV, Low-Power RC Oscillator, or Secondary Oscillator.
The PIC32MZ uses the Peripheral Bus Clock #7 (PBCLK7) to drive the core as SYSCLK.
The default configuration for SYSCLK is programmable and can also be changed at run-time. See the code examples below.
// default system clock = FRCDIV
#pragma config FNOSC = FRCDIV
// default system clock = Primary OSC (XT, HS, EC) with PLL
#pragma config FNOSC = PRIPLL
...
// run-time config SYSCLK = FRCDIV
PLIB_OSC_SysClockSelect(OSC_ID_0, OSC_FRC_BY_FRCDIV);
// run-time config SYSCLK = POSC with PLL
PLIB_OSC_SysClockSelect(OSC_ID_0, OSC_PRIMARY_WITH_PLL);
#pragma config FNOSC = FRCDIV
// default system clock = Primary OSC (XT, HS, EC) with PLL
#pragma config FNOSC = PRIPLL
...
// run-time config SYSCLK = FRCDIV
PLIB_OSC_SysClockSelect(OSC_ID_0, OSC_FRC_BY_FRCDIV);
// run-time config SYSCLK = POSC with PLL
PLIB_OSC_SysClockSelect(OSC_ID_0, OSC_PRIMARY_WITH_PLL);
