PIC32MZ Memory Alignment

Last modified by Microchip on 2023/11/09 09:01

Since the PIC32MZ memory system is 32-bits wide, a data access that is 32-bit (4-bytes, or WORD), or 16-bit (2-bytes, or HALF WORD) in size can either be aligned or unaligned:

  • (Naturally) Aligned Transfer means that the data's address value is a multiple of the data's type size (in bytes)
    • WORD size transfers are carried out to addresses that are a multiple of four: 0x00000000, 0x00000004, 0x00000008, …
    • HALF WORD size transfers are carried out to addresses that are a multiple of two: 0x00000000, 0x00000002, 0x00000004, …
  • Unaligned Transfer means that the data's address does not follow the rules above.

​All MIPS® architectures prior to Release 5 require naturally aligned transfers for normal load/store operations. Unaligned accesses using normal load/store operations will produce exceptions.

​In most cases, C-compilers do not generate unaligned data accesses. It can only happen in:

  • Direct manipulation of pointers
  • Accessing data structures with "packed" attributes that contain unaligned data
  • Inline/Embedded Assembly code

Several examples of naturally aligned and unaligned data transfers are shown in the accompanying image for a MIPS32® Little-Endian memory system:

Memory alignment diagram example