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Step 1: Polling vs Interrupt, NVIC and ISR

Last modified by Microchip on 2026/06/26 07:40

Polling vs Interrupt-Driven Communication

These methods are commonly used for Universal Asynchronous Receiver Transmitter (UART) communication. The polling method results in higher CPU utilization and reduced efficiency for multitasking, as the CPU continuously checks the UART status. In contrast, the interrupt-driven method allows the CPU to execute other tasks and only responds when a UART event triggers an interrupt.

Polling MethodInterrupt-Driven Method
  • In the polling method, the CPU repeatedly monitors the status of the UART peripheral to determine whether it is ready for data transmission or reception.
  • In the interrupt-driven method, the CPU is engaged in various activities, but when an interrupt is triggered, it immediately jumps to execute the Interrupt Service Routine (ISR).
  • The CPU uses up processing time, which decreases its ability to manage other tasks at the same time.
  • The CPU continues working on other tasks until an interrupt is triggered.
  • In the polling method, the response time can be slow.
  • In the interrupt-driven method, the system responds to interrupt events immediately.
  • In polling-based UART communication, the Nested Vectored Interrupt Controller (NVIC) is not required, as the CPU does not rely on interrupts. Instead, the main program continuously monitors the UART status flags to determine data transmission or reception events.
  • The NVIC is essential in the interrupt-driven method; it is responsible for detecting, prioritizing, and dispatching interrupt requests from UART peripherals to the CPU.

 

NVIC

NVIC in the PIC32CM LS00 Curiosity Nano+ Touch Evaluation Kit efficiently manages and prioritizes UART interrupt requests, enabling the CPU to respond immediately to UART transmit or receive events without the need for continuous polling. Each UART interrupt vector is assigned a specific priority level, ensuring that critical communication events are serviced first.

The NVIC supports nested interrupts, allowing higher-priority UART interrupts to preempt lower-priority tasks. This mechanism enhances real-time performance, reduces CPU overhead, and improves system determinism in UART-based embedded applications.

ISR

ISR is a function that executes automatically when an interrupt is triggered. The NVIC manages interrupt prioritization, determining the order in which multiple interrupts are serviced. In this lab, the ISR is implemented as a callback function, which is invoked when the corresponding interrupt event occurs.

The Program Counter (PC) is a special function register that holds the address of the next instruction to be executed.

While the PC is pointing to the current instruction, if an interrupt occurs, program execution is immediately redirected to the corresponding ISR.

When an interrupt is triggered, the current PC value is pushed onto the stack, allowing the CPU to execute the ISR code.

After the ISR completes, the PC is restored from the stack, and program execution resumes from where it was interrupted.

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