SAM L10/L11 Core Overview

Last modified by Microchip on 2023/11/15 13:31

Arm® Cortex®-M23 Processor

The SAM L10 and SAM L11 implement the Arm® Cortex®-M23 processor, based on the Armv8-M Baseline architecture, which is the smallest and most energy-efficient Arm processor with Arm TrustZone® security technology.

The implemented Arm Cortex-M23 is revision "r1p0".

The Arm Cortex-M23 core has two bus interfaces:

  • Single 32-bit AMBA®-5 AHB-Lite system interface that provides connections to peripherals and memories.
  • Single 32-bit I/O port bus interfacing to the PORT and Crypto Accelerator peripherals with 1-cycle load and store.

For more information, refer to the following documents available from Arm:

  • The Arm Cortex-M family now has five processors. "White Paper: Cortex-M for Beginners - An Overview of the Arm Cortex-M Processor Family and Comparison" compares the features of various Cortex-M processors and highlights considerations for selecting a suitable processor for your application. The paper includes detailed comparisons of the Cortex-M instruction sets and advanced interrupt capabilities, along with system-level features, debug and trace features, and performance comparisons.
  • "Armv8-M Architecture Reference Manual" is the specification of the architecture on which the Cortex M23 is based. It covers detailed information about the programmer's model.
  • "Arm Cortex-M23 Devices Generic Users Guide" is targeted at application software developers, it provides information on the programmer's model, details on using the core peripherals such as Nested Vectored Interrupt Controller (NVIC), and general information about the instruction set.
  • "Arm Cortex-M23 Technical Reference Manual" is targeted at silicon designers, this document contains implementation-specific information, such as instruction timing, and some of the interface information.

Cortex-M23 Configuration

This table shows the configurable options for the core and which options are enabled for each family.

Core configurations for each family

Arm Cortex-M23 Core Peripherals

System Timer (SysTick)

The System Timer (SysTick) is a 24-bit timer that extends the functionality of both the processor and the NVIC. Refer to the "Arm Cortex-M23 Devices Generic Users Guide" for details.

Nested Vectored Interrupt Controller (NVIC)

External interrupt signals connect to the NVIC and the NVIC prioritizes the interrupts. The software can set the priority of each interrupt. The NVIC and the Cortex-M23 processor core are closely coupled, providing low-latency interrupt processing and efficient processing of late-arriving interrupts. Refer to the "Arm Cortex-M23 Processor Technical Reference Manual" as well as the "Arm Cortex-M23 Devices Generic Users Guide" for details.

Single-Cycle I/O Port Bus (IOBUS)

The Cortex-M23 processor implements a dedicated, Single-Cycle I/O Port Bus (IOBUS) for high-speed, single-cycle access to certain peripherals. The IOBUS is memory-mapped and supports all the load and store instructions. This bus is used on SAM L10 to provide single-cycle access to the PORT registers.

System Control Block (SCB)

The System Control Block (SCB) provides system implementation information and system control. This includes configuration, control, and reporting of the system exceptions. Refer to the "Arm Cortex-M23 Processor Technical Reference Manual" for details.

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