SAM L10/L11 NVM Controller (NVMCTRL)

Last modified by Microchip on 2023/11/21 20:30

Non-Volatile Memory Controller (NVMCTRL)


Non-Volatile Memory (NVM) is a reprogrammable Flash memory that retains program and data storage even with power off.

It embeds three separate arrays, FLASH, Data FLASH, and NVM Rows.

The Data FLASH array can be programmed while reading the FLASH array. It is intended to store data while executing from the FLASH without stalling.

NVM Rows store the data needed during the device startup such as calibration and system configuration.

The NVM Controller (NVMCTRL) connects to the Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) interfaces for system access to the NVM block. The AHB interface is used for reads and writes to the NVM block, while the APB interface is used for commands and configuration.


  • 32-bit AHB interface for reads and writes
  • Write-While-Read (WWR) Data Flash
  • All NVM sections are memory mapped to the AHB, including calibration and system configuration
  • 32-bit APB interface for commands and control
  • Programmable wait states for read optimization
  • Six regions can be individually protected or unprotected
  • Additional protection for bootloader
  • Interface to power manager for power-down of Flash blocks in Sleep modes
  • Can optionally wake up on exit from sleep or on first access
  • Direct-mapped cache
  • Arm® TrustZone® technology support (SAM L11)

Block Diagram

SAM L10 NVM controller block diagram

​Refer to the "NVMCTRL – Nonvolatile Memory Controller" chapter from the product datasheet for more details.

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