SAM L10/L11 Reset Controller (RSTC)

Overview

The Reset Controller (RSTC) manages the Reset of the microcontroller. It issues a microcontroller Reset, sets the device to its initial state and allows the Reset source to be identified by software. The RSTC collects the various Reset sources and generates a Reset signal for the device. After a Power-on Reset (POR), the RSTC is enabled and the Reset Cause (RCAUSE) register indicates the POR source. The RSTC module is always enabled and is active in all Sleep modes.

Features

• Reset the microcontroller and set it to an initial state according to the Reset source
• Reset the cause register for reading the Reset source from the application code
• Multiple Reset sources
  • Power supply Reset sources: Power-on Reset (POR), Brown-Out-Detection (BOD12, BOD33)
  • User Reset sources: External Reset (RESET), Watchdog Reset, and System Reset Request

Block Diagram

SAM L11 TrustZone^® Specific Register Access Protection

On SAM L11 devices, this peripheral has different access permissions depending on Peripheral Access Controller (PAC) Security Attribution (Secure or Non-Secure):

• If the peripheral is configured as Non-Secure in the PAC:
  • Secure access and Non-Secure access are granted
• If the peripheral is configured as Secure in the PAC:
  • Secure access is granted
  • Non-Secure access is discarded (writes are ignored, reads return 0x0) and a PAC error is triggered

Principle of Operation

The latest Reset cause is available in the RCAUSE register and can be read during the application boot sequence in order to determine the proper action.

Reset sources fall into the following groups:

• Power supply Resets: Those caused by an electrical issue (covers POR and BODs Resets)
• User Resets: Those caused by the application (covers External Resets, System Reset Requests and Watchdog Resets)

The following table lists the parts of the device that are reset, depending on the Reset type.

The external Reset is generated when pulling the RESET pin low.

• The POR, BOD12, and BOD33 Reset sources are generated by their corresponding module in the Supply Controller (SUPC).
• The WDT Reset is generated by the Watch Dog Timer (WDT).
• The System Reset Request is a Reset generated by the CPU when asserting the SYSRESETREQ bit located in the Reset Control register of the CPU (for details refer to the Arm^® Cortex^®-M23 Processor Technical Reference Manual).

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