SAM L10/L11 Watchdog Timer (WDT)

Last modified by Microchip on 2023/11/21 20:25


The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset.

An early-warning interrupt is available to indicate an upcoming watchdog time-out condition.

The Window mode makes it possible to define a time slot (or window) inside the total time-out period during which the WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will be issued. Compared to Normal mode, this can also catch situations where a code error causes the WDT to be cleared frequently.

When enabled, the WDT will run in Active mode and all Sleep modes. It is asynchronous and runs from a CPU-independent clock source. The WDT will continue operation and issue a system reset or interrupt even if the main clocks fail.

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  • Issues a system reset if the WDT is not cleared before its time-out period
  • Early Warning Interrupt generation
  • Asynchronous operation from a dedicated oscillator
  • Two types of operation
    • Normal mode
    • Window mode
  • Selectable time-out periods
    • From eight cycles to 16,384 cycles in Normal mode
    • From 16 cycles to 32,768 cycles in Window mode
  • Always-On capability

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Block Diagram

SAM L10 watch dog timer block diagram

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Principle of Operation

When enabled, the WDT is a constantly running timer that is configured to a predefined time-out period. Before the end of the time-out period, the WDT should be set back, or else a system Reset is issued. The WDT has two modes of operation, Normal mode and Window mode. Both modes offer the option of Early Warning Interrupt generation. The settings in the Control A (CTRLA) register and the Interrupt Enable register (handled by INTENCLR, INTENSET registers) determine the mode of operation.

The WDT bus clock (CLK_WDT_APB) can be enabled and disabled (masked) in the Main Clock (MCLK) module. A 1.024 kHz oscillator clock (CLK_WDT_OSC) is required to clock the WDT internal counter. The CLK_WDT_OSC clock is sourced from the clock of the internal Ultra Low-Power Oscillator (OSCULP32K). Due to the ultra-low power design, the oscillator is not accurate, hence the exact time-out period may vary from device-to-device. This variation must be considered when designing software that uses the WDT to ensure that the time-out periods used are valid for all devices. The counter clock (CLK_WDT_OSC) is asynchronous to the bus clock (CLK_WDT_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains.

The interrupt request line is connected to the interrupt controller. Using the WDT interrupt(s) requires the interrupt controller to be configured first.

The WDT is cleared and a new WDT time-out period is started by writing "0xA5" to the CLEAR register. Writing any other value than "0xA5" to CLEAR will issue an immediate system reset.

​Refer to the WDT chapter from the product datasheet to get more details.

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