SAM L10/L11 Power Gating

Last modified by Microchip on 2023/11/16 19:28

Power Gating Overview

Power Gating is an extension to SleepWalking, which adds the capability to enable a power domain (in addition to the clock gating) from retention to active state (on the fly and automatically) to save power in Standby Low-Power mode. This means that a power domain will only be active when a peripheral within it needs to be active.

The SAM L10/L11 architecture allows the implementation of the Power Gating feature through power domain partitioning, represented in the following figure.

SAM L10 power gating power domains architecture

In addition to the supply domains, such as VDDIO and VDDANA, the device provides these power domains:

  • PDSW
  • PDAO

PDSW is a Switchable Power Domain. In Standby Sleep mode, it can be turned off to avoid leakage consumption according to the user configuration. It contains the Event System, Generic Clock Controller, Main Clock Controller, Oscillator Controller, Non-Volatile Memory Controller, Direct Memory Access Controller (DMAC), Device Service Unit, and the ARM® core. PDSW also contains several peripherals that allow the device to wake up from an interrupt: Serial Communication Interface (SERCOM), Timer, Analog-to-Digital Converter (ADC), Digital-to-Analog Converter (DAC), Operational Amplifier Controller (OPAMP), Configurable Custom Logic (CCL), and the Peripheral Touch Controller (PTC).

PDAO is the Always-On Power Domain, it contains all controllers that are always powered when in Active, Idle, or Standby mode.

Related Peripherals

The related peripheral to control the Voltage Regulator is the Power Manager.

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Static or Dynamic Power Gating

By default, when entering Standby Sleep mode, the power domain PDSW is set in retention state. This allows for a very low power consumption while retaining all the logic content of these power domains. When exiting Standby mode, all power domains are set back to an active state.

There are two types of power gating in the SAM L10/L11 product family: Static and Dynamic.

Static Power Gating

Static Power Domain Gating is a technique that automatically turns off the PDSW power domain supply when not used while keeping PDAO powered up. This Static Power Domain Gating feature is active by default and is supported by all peripherals. For some peripherals, it must be enabled by writing a "Run in Standby" bit in the respective Control A register (CTRLA.RUNSTDBY) to '1'.

Static Power Gating

From the Static Power Gating chart, the PDSW is always ON as the ADC and the Direct Memory Access (DMA) relate to this Power Domain. Otherwise, if the peripheral that is not related to the PDSW Power Domain would have been used, the chart should have shown the PDSW in retention.

Dynamic Power Gating

The power domain PDSW can be automatically controlled (active or retention state) depending on peripheral requirements (PDCFG bit from the STDBYCFG register) to control power gating in addition to clock gating (e.g., used in SleepWalking).

Dynamic power gating

From the Dynamic Power Gating chart, the PDSW switching corresponding to the ADC/DMA clocks requests can be observed.

The Dynamic Power gating can be based on peripheral event system or Peripheral DMA Trigger.

To enable the Dynamic Power Gating for Power Domain, DPGPDSW bit in the Standby Configuration register of the Power Manager (PM) (STDBYCFG.DPGPDSW) has to be written to 1.

Code Example Enabling the Dynamic Power Gating

/*** (PM_STDBYCFG) Dynamic Power Gating enabled ***/

​The Power Domain mode is configured through the Power Domain Controller. Refer to the "Ultra Low-Power, 32-bit Cortex-M23 MCUs with TrustZone, Crypto, and Enhanced PTC" SAM L10/L11 family datasheet for more details.

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