SAM L10/L11 Voltage Regulators

Overview

The SAM L10/L11 embeds two voltage regulators that are used to provide VDDCORE to the device.

• The main voltage regulator (MAINVREG) has two modes related to two types of regulators in Active mode:
  • Linear Low-Dropout (LDO) type (selected by default after a device reset)
  • Switching (Buck Converter) type
• A Low-Power Voltage Regulator in Standby mode (LPVREG)
  • Selected by default when the device is in Standby Sleep mode

Related Peripherals

The related peripheral to control the voltage regulator is the Supply Controller.

Main Voltage Regulator

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Regulator Type Selection

In Active mode, the type of the main voltage regulator supplying VDDCORE can be switched on the fly between an LDO-type regulator or a Buck-type converter.

The main voltage regulator switching sequences are as follows:

• The user changes the value of the Voltage Regulator Selection bit in the Voltage Regulator System Control register (VREG.SEL).
• The start of the switching sequence is indicated by clearing the Voltage Regulator Ready bit in the STATUS register (STATUS.VREGRDY = 0).
• Once the switching sequence is completed, STATUS.VREGRDY will read 1.

The Voltage Regulator Ready (VREGRDY) interrupt can also be used to detect a zero-to-one transition of the STATUS.VREGRDY bit.

Differences Between Switching and Linear Regulators

LDO linear regulators use non-switching techniques to regulate the voltage output from the power supply. The regulator’s resistance varies according to the load and results in a constant output voltage. All linear regulators require an input voltage at least some minimum amount higher than the desired output voltage. That minimum amount is called the dropout voltage. An LDO regulator is a DC linear regulator that can regulate the output voltage even when the supply voltage is very close to the output voltage. This is a good choice for powering applications or devices where the difference between the input and the output voltage is small. An LDO is less efficient than a switching regulator in terms of power conversion and power capacity/dissipation, but the usage of an LDO regulator is quite simple and cheap, and it perfectly fits with Low Noise application requirements.

On the other hand, switching regulators rapidly switch a series element on and off. They can operate with both synchronous and non-synchronous switches (FETs). These devices store the input energy temporarily and then release that energy to the output at a different voltage level. The switch’s duty cycle sets the amount of charge transferred to the load. Switching regulators are efficient because the series element is either fully conducting or switched off so it dissipates almost no power. Switching regulators are able to generate output voltages that are higher than the input voltage or of opposite polarity, unlike linear regulators. The drawback of using a switching regulator implies a more complex design to reduce as much as possible the noise effect coming from the switching activity.

Low-Power Voltage Regulator (LPVREG)

This regulator is automatically used when the device enters into Standby Low Power mode.

Low Power Efficiency

By writing the Low-Power mode efficiency bit in the VREG register (VREG.LPEFF) to 1, the efficiency of the regulator in LPVREG can be improved when the application uses a limited VDD range (2.5 to 3.63V). It is also possible to use the BOD33 in order to monitor the VDD and change this LPEFF value on the fly according to the VDD level.

Low-Power VREF in Active Mode

During the Active Functional mode, the brownout detector BOD33 and the main voltage regulator (VREG) can reduce their power consumption by using a low power voltage reference (ULPVREF). The LPVREG is started after power-up and is available when the ULPVREFRDY bit in the STATUS register is high. Writing the VREF bit in the BOD33 register to '1' selects ULPVREF as a voltage reference for the BOD33.

If the chip operates in Performance Level mode PL0 (PM->PLCFG.PLSEL = 0) or Performance Level mode is disabled (PM->PLCFG.PLDIS = 1), writing the VREFSEL bit in the VREG register to 1 selects ULPVREF as the voltage reference for the main voltage regulator.

Code Example Configuring the Regulator in Low Power Mode Having the Best Power Efficiency

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Voltage Scaling

The VDDCORE supply will change under certain circumstances:

• When a new performance level (PL) is set
• When the Standby Sleep mode is entered or left
• When a sleepwalking task is requested in Standby Sleep mode

To prevent high peak current on the main power supply and to have a smooth transition of VDDCORE, both the voltage scaling step size and the voltage scaling frequency can be controlled.

VDDCORE is changed by the selected step size (VREG.VSVSTEP) of the selected period (VREG.VSPER) until the target voltage is reached.
The following waveform shows an example of changing performance levels from PL0 to PL2.

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