Learn About Timer/Counter Type E (TCE)

Last modified by Microchip on 2024/06/17 10:49

The Timer/Counter Event (TCE) system is a powerful peripheral designed to provide precise timing and event-counting capabilities, which are essential for a wide range of embedded applications.

Timer Counter Type E Block Diagram


  • Multiple Channels: The TCE peripheral typically offers multiple independent channels that can be configured for different tasks, allowing for concurrent operations like timing, event counting, or pulse generation.
  • Flexible Clocking Options: It supports various clock sources, including internal system clocks and external inputs.
  • Configurable Modes: The TCE peripheral can operate in several modes:
    • Normal: The counter increments until it matches the compare value then resets. This mode is used to generate interrupts on a regular interval.
    • Frequency: The counter counts in one direction and resets when it reaches the period value. The waveform output toggles when the counter reaches 0x0000 or the value in the period register.
    • Single Slope: The counter counts in one direction and resets when it reaches the period value. The waveform output is driven high when the counter value matches the compare value and driven low when it matches the period value. The waveform can also toggle on period boundaries depending on the compare value. See “Learn About Timer/Counter Type E Single Slope Mode” for details.
    • Dual-Slope: The counter counts in both directions and changes direction when it reaches 0x000 or the period value. The waveform output is driven low on the first match and high on the second match. The waveform can also toggle on period boundaries depending on the compare value.
  • Double Buffered Duty Cycle and Period Register: The Period and Compare registers have corresponding buffer register that can be written any time. These values are loaded into their respective control register at the end of the next cycle to eliminate uncontrolled waveform output transitions.
  • Automatic Port Override: The associated waveform output pin is automatically overridden when its associated compare module is enabled simplifying setup.
  • Timer/Counter Commands: The software can issue a command set to change the peripheral state immediately. These commands give direct control of the UPDATE, RESTART and RESET signals.
  • High Resolution Mode: The high resolution can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, Single-Slope PWM, or Dual-Slope PWM generation. It can also be used with the WEX if used for the same timer/counter.
  • Automated Amplitude and Offset Available: Four methods are available to adjust the waveform output’s amplitude and offset.
  • Fractional Compare Values: Compare values can be written as a fractional value based on the UQ1.15 format.
  • Easy Waveform Extension (WEX) Integration: WEX can add deadband, swap and pattern generation capabilities to waveforms.

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Use Cases

  • Motor Control: The PWM capabilities of the TCE can be used to control the speed and direction of DC or stepper motors.
  • Event Counting: The counter mode can be used to count external events, such as revolutions of a wheel or items passing on a conveyor belt.
  • Signal Generation: The TCE can generate regular waveforms for use in signaling, tone generation, or as a clock source for other peripherals.

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Timer Counter Type E Waveform with Match and Update Events

Note: This waveform represents Single-Slope Mode. The definitions for MATCH, TOP, UPDATE and OVF depend on the mode selected. See the "Modes" section for details.

Term                 Description
CLK_PERThis is a clock input source for the TCE peripheral. It’s a software-controlled divider based on the system clock controlled by the CLKSEL[2:0] bits.
Event SystemAn internal MCU system for direct peripheral-to-peripheral signaling where peripherals can directly produce, use and react to peripheral events.
Period Register (PER)This register holds the value that determines the period of the PWM frequency. The period is the duration of one complete cycle of the PWM signal, which includes both the "on" time (pulse width) and the "off" time.
Period Buffer (PERBUF)The PERBUF is used to double buffer the period value. It permits changes to the PWM period while the current cycle is still running.  The new value from PERBUF is transferred to the PER register when the UPDATE condition occurs thereby preventing glitches in the PWM signal.
Compare Register (CMP)This register holds a value that is continuously compared against the value of the CNT register. When the CNT register's value matches the value in the CMPn register, an action is taken, such as toggling the output of the PWM signal from high to low or vice versa, generating an interrupt, etc. depending on the configuration.
Compare Buffer (CMPBUF)Similar to the PERBUF, the CMPBUF is used to double buffer the compare value. This allows updates to the duty cycle to be made without causing unexpected changes to the output signal. The new value written to the CMPBUF is transferred to the CMP register at a specific time, often at the start of a new PWM cycle, to ensure a smooth transition and to maintain signal integrity.
Count Register (CNT)The count register is incremented (or decremented, depending on the configuration) with each clock cycle or event. When the count matches the value in the PER register, the waveform output is driven low, starting a new cycle. An interrupt can be generated when this event occurs.
BOTTOMThis event denotes when the 16-bit CNT Register reads 0x0000.
MAXThe counter register, CNT, value of 0xFFFF.
TOPThis is the value in the Period Register.
MATCHThis event indicated when the CNT register value matches one of the comparator values (CMPn).
UPDATEThis event occurs when the CNT Register value matches the PER Register (TOP) value. When an Update Event occurs, it prompts the transfer of values from the PERBUF and CMPBUF registers into the corresponding Period (PER) and Compare (CMP) registers. This drives the waveform output low if it isn’t already low.
Waveform Output (WOn)The associated pin(s) for TCE peripheral waveform output, e.g. WO0, WO1, etc.
OVFAn interrupt flag that indicates the Counter Value (CNT) has reached a TOP or BOTTOM threshold.

Timer Counter Type E Waveform with Wrap-Around Event

Wrap-around EventWhen the Counter Value (CNT) is updated to a value higher than TOP and resets when it reaches MAX or BOTTOM value.
DIRA register bit that selects whether CNT Register counts up or down.

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Waveforms are selected using the WGMODE[2:0] bit. Each mode has its own unique set of definitions for MATCH, TOP, UPDATE and OVF. Here is a summary of the definitions:

WGMODE[2:0]Group ConfigurationMode of OperationMATCHTOPUPDATEOVF
000NORMALNormal (Interrupt only)-PERTOP/BOTTOM*TOP/BOTTOM*

Note: TOP is used when CNT counts up and BOTTOM when CNT counts down based on DIR bit setting.

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The TCE supports 5 different interrupts, each with a dedicated interrupt flag in the INTFLAGS register and enable bit located in the INTCTRL register.

OVFOverflow or underflowCNT register value reached TOP or BOTTOM
CMP0Compare Channel 0Match between CNT Register value and CMP0 Register
CMP1Compare Channel 1Match between CNT Register value and CMP1 Register
CMP2Compare Channel 2Match between CNT Register value and CMP2 Register
CMP3Compare Channel 3Match between CNT Register value and CMP3 Register

In summary, the TCE peripheral is a powerful and flexible tool that can be adapted to a wide range of timing, counting, and control applications. Its multiple modes and features enable developers to implement complex functionalities with a single hardware component, optimizing both the performance and the cost-effectiveness of their embedded systems.

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