Learn About Timer/Counter Type E Single Slope Mode

Last modified by Microchip on 2024/06/17 10:51

The Timer Counter Type E (TCE) peripheral is a versatile hardware component commonly found in microcontrollers and embedded systems. It is designed to handle a variety of timing and counting tasks with high precision and flexibility. One of the operational modes supported by the TCE is the Single Slope Mode, which is particularly useful for generating waveforms, measuring time intervals, and controlling event timing.

Use Cases for Single Slope Mode

  • Pulse Width Modulation (PWM) Control for Motors: single Slope Mode is often used to generate PWM signals for controlling the speed of DC motors. By adjusting the duty cycle, the average voltage applied to the motor changes, thereby controlling its speed.
  • LED Dimming: in lighting applications, Single Slope Mode can be used to dim LEDs by varying the duty cycle of the PWM signal. This allows for precise control over the brightness of the LED without changing the voltage.
  • Tone Generation: audio applications can utilize Single Slope Mode to generate tones of specific frequencies. By setting the counter's maximum value, the frequency of the output waveform can be controlled, which in turn can be used to produce different tones.
  • Servo Motor Control: the precise timing control offered by Single Slope Mode is ideal for controlling the position of servo motors. The width of the PWM pulse dictates the angle to which the servo arm moves.
  • Time Measurement: Single Slope Mode can be used in applications that require time measurement, such as in ultrasonic distance sensors. The time taken for a pulse to return can be measured by the counter, which can then be used to calculate distance.
  • Frequency Generation: for applications that require a stable frequency output, such as clock generation or signal processing, Single Slope Mode can be configured to produce a consistent frequency signal.

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In Single Slope Mode, the TCE peripheral period is defined by counting clock pulses in the Counter Register value (CNT) register from 0 up to a maximum value, TOP, at which point the counter resets to the starting value, and the cycle repeats. The duty cycle is defined by a match in the counter value and one of the four comparator register values (CMPn). This mode is called single slope because the CNT increases or decreases in a single direction (depending on DIR bit setting) before resetting, resembling a ramp in its waveform representation. PWM signals are essential in controlling the power delivered to devices such as motors and LEDs, where the duty cycle of the waveform (the proportion of time the signal is high versus low) determines the power level.

Timer Controller Type E Update and Match Waveform

Note: In this diagram, the compare register (CNT) is counting up as DIR bit = 0.

Waveforms are selected using the WGMODE[2:0] bit. Each mode has its own unique set of definitions for MATCH, TOP, UPDATE and OVF. Single Slope Mode is selected by setting WGMODE[2:0] to 0b011. Single Slope Mode uses the PER register for TOP, CMPn for MATCH and the BOTTOM register for UPDATE and OVF. Refer to the "Terminology" section of the "Learn About Timer/Counter Type E (TCE)"  page for definitions.

WGMODE[2:0]Group ConfigurationMode of OperationMATCHTOPUPDATEOVF
000NORMALNormal (Interrupt only)-PERTOP/BOTTOM*TOP/BOTTOM*

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Setting the PWM Period

In Single Slope Mode, the Period Register (PER) and associated Period Buffer (PERBUF) in the TCE peripheral are used to control the period time of the Waveform Output. As the Counter Register, CNT, increments, an UPDATE event will occur when its value matches TOP as defined by the PER register. At this time, the associated Waveform Output (WOn) is driven high if the CMPn value is greater than BOTTOM (0x0000).

Here’s how PER, CMPn, CNT, UPDATE, MATCH, TOP, and BOTTOM tie together to control the Waveform Output (WOn) period:

Timer Counter Type E Waveform with Match and Update Events

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Configuring the PWM Duty Cycle

The Compare (CMP) and Compare Buffer (CMPBUF) registers define the duty cycle of a Waveform Output. When the Counter Register, CNT, matches a Comparator Register (CMPn) value, the associated Waveform Output (WOn) is driven low.

Here’s how PER, CMP, CMPBUF, CNT, UPDATE, MATCH, TOP and BOTTOM work together to control the Waveform Output (WOn) duty cycle:

Timer Counter Type E Compare Register Changes Waveform

Note: Waveform period and duty cycle updates at runtime will be immediate when writing the PER and CMPn registers and can result in irregular waveforms. To avoid this, perform updates to PERBUF and CMPnBUF registers instead.

By adjusting the value in the CMP register, and queuing changes in the CMPBUF, you can precisely control the duty cycle of the PWM signal. This is essential for applications where the amount of power delivered to a load needs to be controlled, such as in motor speed control, where the duty cycle determines the speed of the motor, or in LED dimming, where it determines the brightness of the light.

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Initialization Sequence

The following initialization sequence for the TCE in Single Slope Mode. It is highly recommended to use MPLAB® Melody Code Configurator to simplify TCE setup. To see an example, refer to the "How To Generate 4 PWM Channels Simultaneously Using AVR® Timer Counter Type E" page.

  1. Enable TCE Module by setting the ENABLE bit.
  2. Select a system clock source divider using the CLKSEL[2:0] bits to divide by 1, 2, 4, 8, 16, 64, 256 or 1024.
  3. Select a count direction with the DIR Counter Direction bit.
  4. Use the WGMODE[2:0] Waveform Generation Mode bits to select SINGLESLOPE.
  5. Request a period using the 16-bit Period Register, PER[15:0].
  6. Request duty cycles by writing the associated 16-bit CMPn[15:0] registers.
  7. Verify actual period and duty cycles are acceptable*.
  8. Enable waveform outputs by setting the associated CMPnEN Compare Enable bit(s).
  9. Select whether waveform(s) will be inverted via the CMPnPOL Compare n Polarity bits.
  10. Choose resolution and scaling options with the HREN[1:0] High Resolution Enable bits and SCALEMODE[1:0] Scale Mode bits.
  11. If interrupts are needed, set the Comparator Interrupt using CMPn and/or the Timer Overflow/Underflow Interrupt Enable bit, OVF, bit in the Interrupt Control Register.

Note: MPLAB Melody will show actual period and duty cycles for comparison.

In summary, the Single Slope Mode of the TCE peripheral is a fundamental tool for developers working on embedded systems. Its ability to generate precise timing signals and PWM outputs makes it invaluable in a wide range of applications, from motor control to signal processing.

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