Last modified by Microchip on 2023/11/10 11:09

The main function of the AVR® Central Processing Unit (CPU) core is to ensure correct program execution. The CPU must, therefore, be able to access memories, perform calculations, control peripherals, and handle interrupts.

AVR Core

AVR Core

In order to maximize performance and parallelism, the AVR uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.


The fast-access Register file contains 32 x 8-bit General Purpose Working registers with a single clock cycle access time. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-registers.

Arithmetic Logic Unit (ALU)

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single clock cycle access time allows single-cycle ALU operations. In a typical ALU operation, two operands are output from the Register file, the operation is executed and the result is stored back in the Register file in one clock cycle. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.


The memory spaces in the AVR architecture are all linear and regular memory maps.

Program Flash memory space is divided into two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The Store Program Memory (SPM) instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM and consequently, the stack size is only limited by the total SRAM size and the usage of the SRAM.

All user programs must initialize the Stack Pointer (SP) in the Reset routine (before subroutines or interrupts are executed). The SP is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control registers, Serial Peripheral Interface (SPI), and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register file, 0x20 - 0x5F. In addition, this device has extended I/O space from 0x60 - 0xFF in SRAM.


A flexible Interrupt module has its Control registers in the I/O space with an additional Global Interrupt Enable bit in the Status register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.