How to Drive a 7-segment Display
Overview
7-segment displays are widely used in applications like digital clocks, temperature displays and basic user interfaces where numeric or limited alphanumeric data needs to be visually represented. This page demonstrates how to use the Configurable Logic Block (CLB) to drive a 7-segment display, reducing external components and freeing up the CPU for other operations.
Each segment (Segment A, Segment B, etc.) of the 7-segment display requires its own control signal, which is generated by the microcontroller’s I/O pins. The CLB processes a 4-bit Binary Coded Decimal (BCD) input, representing a single digit (0–9), and decodes it into the seven control signals. This ensures the appropriate segments light up to display the desired output.
The CLB can be utilized to drive a 7-segment display using a 4-bit Binary Coded Decimal (BCD) input. A primary design challenge is that a 4-bit BCD input cannot directly drive the individual segments of the display. The CLB overcomes this by implementing custom hardware logic that seamlessly converts the BCD input into the precise control signals needed for each segment.
Verilog Code for bcd7Seg Module:
bcd0, bcd1, bcd2, bcd3,
seg0, seg1, seg2, seg3, seg4, seg5, seg6
);
input bcd0, bcd1, bcd2, bcd3; // initializing bcd as a 4-bit input signal
output seg0, seg1, seg2, seg3, seg4, seg5, seg6; // initializing seg as a 7-bit output signal
assign seg0 = ~(((~bcd3)&(~bcd2)&(~bcd1)&bcd0) | ((~bcd3)&bcd2&(~bcd1)&(~bcd0))); // Logical expression for segment A
assign seg1 = ~(((~bcd3)&bcd2&(~bcd1)&bcd0) | ((~bcd3)&bcd2&bcd1&(~bcd0))); // Logical expression for segment B
assign seg2 = ~(((~bcd3)&(~bcd2)&bcd1&(~bcd0))); // Logical expression for segment C
assign seg3 = ~(((~bcd3)&(~bcd2)&(~bcd1)&bcd0) | ((~bcd3)&bcd2&(~bcd1)&(~bcd0)) | ((~bcd3)&bcd2&bcd1&bcd0)); // Logical expression for segment D
assign seg4 = ~(((~bcd3)&bcd0) | ((~bcd3)&bcd2&(~bcd1)) | (~(bcd2)&(~bcd1)&bcd0)); // Logical expression for segment E
assign seg5 = ~(((~bcd3)&(~bcd2)&bcd0) | ((~bcd3)&(~bcd2)&bcd1) | ((~bcd3)&bcd1&bcd0)); // Logical expression for segment F
assign seg6 = ~(((~bcd3)&(~bcd2)&(~bcd1)) | ((~bcd3)&bcd2&bcd1&bcd0)); // Logical expression for segment G
endmodule
Requirements
- CLB peripheral
- 7-segment display
- Resistors (one resistor per segment)
- Find a Part - Microcontroller and Processor Products Page
Procedure
Implement the CLB logic by creating a Verilog sheet in the CLB Synthesizer tool to define the logic for driving the 7-segment display. This Verilog code decodes the 4-bit BCD input into the seven control signals required to drive the display segments. Refer to the block diagram above for guidance.
Assign pins by mapping the 4-bit BCD input signals to the appropriate input connections. Route the seven decoded output signals from the CLB to the corresponding connections for the segments (Segment A, Segment B, etc.) of the 7-segment display.
To ensure the 7-segment display functions correctly, the source code in the main application must provide input values to the CLB. This can be done by cycling through values dynamically, such as 0–9 for the 7-segment display.
Here is a code example of software-based input to the CLB:
for(uint8_t i = 0; i < 10; i++) {
CLB1_SWIN_Write(i); // Send BCD input to CLB
_delay_ms(250); // Add a delay to make the output visible
}
}
Verify the design by testing the 7-segment display to ensure each BCD input (0–9) activates the correct segments. Use a debugging tool or simulation to confirm that the CLB outputs match the expected segment patterns and that the display operates smoothly without errors.
Results
The GIF demonstrates the 7-segment display cycling through digits 0–9, with each digit accurately represented by the correct combination of illuminated segments. This confirms that the CLB logic successfully decodes the 4-bit BCD inputs into segment control signals. The smooth transitions and proper representation validate the design and its intended functionality.
