CLCxSELn Registers

The CLCxSEL Registers, contained in the Configurable Logic Cell (CLC), control which inputs are used with the CLC.

CLC Input Sources

The CLC will have multiple inputs to select from and each will have a 3-bit code associated with it, as shown in the accompanying table. Each input can be connected to one of the two input data gates through a multiplexer that is controlled by the CLCxSEL0 and CLCxSEL1 registers.

The Input Selections are controlled by the CLCxSEL0 and CLCxSEL1 registers by setting the input 3-bit code.

• The CLCxSEL0 register controls the data input gates 1 and 2. Bits 0-2 control input 1 and bits 4-6 control input 2.

CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER

The CLCxSEL1 register controls the data input gates 3 and 4. Bits 0-2 control input 3 and bits 4-6 control input 4.

CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER