dsPIC33A 12-bit 40MSPS Analog-to-Digital Converter (ADC) Deep Dive
Performance Summary
Last modified by Microchip on 2026/03/31 11:43
| DSP Performance: dsPIC33AK512MPS510 | System Resources |
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If you compare the dsPIC33A Analog-to-Digital Converter (ADC) with the previous dsPIC33C ADC, the new ADC has:
- Significantly less latency
- Can work with the signal sources having much higher impedance
- Allows selection of a different sampling time for each converted input
- Has more result accumulators and comparators
| Performance Feature | dsPIC33AK512MPS512 | Benefits - Comments |
|---|---|---|
| Number of analog conversion cores | Five 40 Msps cores | Flexible, powerful min. digital delays |
| Typical signal source impedance | 100Ω (CHOLD = ~1 pF) | Minimize need for external buffer |
| Sampling time selection | Selectable for each input | Optimize data channel throughput |
| Inputs conversion priority/order | Programmable | Flexible prioritization in hardware |
| Conversion result comparators | 48 (one HI/LOW set per data channel) | Customized data monitors |
| Result accumulators | 48 (one per data channel) | Support of multi-sample modes |
| Trigger selection | Set for each data channel, individually | Tailorable for each data channel |
| Effective Number of Bits (ENOB) | Typ. 10.5b | Solid ENOB for a wide range of apps |
| INL error (max) | 3 LSb | Monotonicity guaranteed |
| DNL error (min) | 2 LSb | Monotonicity guaranteed |
| Offset error (typ.) | 5 LSb | Internal hardware to calibrate |
| Gain error (max) | 5 LSb | Adjust with gain error calibration |
| Offset calibration method | Startup hardware calibration ~5,000 TAD cycles | Calibration includes both gain and offset adjustments |