dsPIC33A 12-bit 40MSPS Analog-to-Digital Converter (ADC) Deep Dive

Digital Comparators

Last modified by Microchip on 2026/03/31 11:17

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Digital Comparator Block Diagram

Each data channel in the Analog-to-Digital Converter (ADC) has a digital comparator. And each of these comparators includes limit registers with adjustable upper and lower thresholds, enabling real-time monitoring and robust application safeguards.

Data channel results are compared to these user-defined limits to detect:

  • Out-of-bounds (outside lower/upper limits)
  • In-bounds (within both limits)
  • Greater than or equal to the lower limit
  • Less than or equal to the upper limit

Each data channel can trigger a comparator interrupt after a user-defined number of matches.

The digital comparators work with 32-bit data and support both immediate and averaged results, selectable via the CMPVAL bit.

The digital comparator can function with any of the ADC sampling modes: Single, Oversampling, Windowed, and Integration. The requirement is that the comparator limit register must match the result format. In Single and Oversampling modes, this can be integer or fractional (set by FRAC bit). In Windowed or Integration modes, it will always be an integer.

This feature is ideal for implementing application safeguards and real-time data channel monitoring.