dsPIC33A Digital Signal Processing (DSP) Engine

Last modified by Microchip on 2025/02/03 14:52

Overview

The dsPIC33A core seamlessly executes DSP-class instructions using a Digital Signal Processing (DSP) engine that provides several key features.

Key Features

  • A high-speed, 33-bit by 33-bit multiplier
  • A 72-bit Arithmetical Logical Unit (ALU)
  • Two 72-bit saturating accumulators
  • A 72-bit bidirectional barrel shifter, capable of shifting a 40-bit value up to 32 bits right, or up to 32 bits left, in a single cycle

Block Diagram

DSP Engine diagram

The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two working registers. This requires that the data space be split for these instructions and linear for all others. This is achieved in a transparent and flexible manner through dedicating certain working registers to each address space.