dsPIC33A Instruction Set Architecture
Overview
The Instruction Set Architecture (ISA) of a Central Processing Unit (CPU) refers to the lowest-level interface between the programmer and the CPU, and includes the following aspects:
- Datatypes
- Supported operand representations
- Operations on data
- Arithmetic or other operations that can be performed on the operands
- Instruction format
- Memory organization
- Addressing modes
This page provides an overview of the dsPIC33A ISA. For more details, please refer to the "dsPIC33A Programmer's Reference Manual."
Memory Organization
The dsPIC33A contains several distinct memory regions, which are arranged in a 16 MB addressable unified memory map:
The first 64 kB of memory addresses data Random-Access Memory (RAM) and Special Function Registers (SFRs). The term "near" refers to a memory region whose address can be encoded as a 16-bit value in the instruction opcode. Some instructions can encode a 20-bit address (1 MB) in the opcode and thus can access the "far data" memory region.
Detailed device-specific memory maps are provided in the device datasheet.
Instruction Addressing
Most dsPIC33A instruction words are 32-bits wide, with some half-word (16-bit) and double-word (64-bit) instructions. The Program Counter (PC) is 24 bits wide and can address the entire 16 MB memory space, enabling instruction access from data memory (RAM). The PC is incremented by two, four, or eight during sequential 16-bit, 32-bit, or 64-bit instruction execution, respectively.
By default, code execution begins at the address specified in the reset vector at 0x800000.
Data Addressing
Different CPU instructions have different address ranges. This depends on the number of address bits that can be encoded:
- File register addressing encodes address bits directly in the opcode. Most of these instructions can address 64 KB (16 bits) and a few can access 1 MB (20 bits), starting at address 0x000000.
- Register indirect addressing can address the entire 16 MB space (24 bit address) since it is using a 32-bit register (value truncated to 24 bits) as a pointer.
Registers
CPU Core Registers
dsPIC33A devices have 16x32-bit W-Regs and 2x72-bit accumulators. They also include seven alternate contexts, one per Interrupt Priority Level (IPL), for W0-W7 and seven alternate contexts for the 2x72-bit accumulators, RCOUNT and CORCON:
FPU Registers
The Floating-Point Unit (FPU) is a hardware module that follows a load-store architecture and is designed to provide a complete IEEE 754-2019 compliant FPU with support for single and double precision. With the addition of the FPU, the CPU now fetches instructions, decodes them and issues floating-point operations to the FPU. The FPU then executes the instruction using its own independent load-store instruction pipeline. This allows both the CPU and FPU to execute their respective instructions concurrently, provided there are no data hazards that stall the pipeline. Since the CPU and FPU are separate, FPU operands and results are local to the FPU. The CPU moves data to and from the FPU using dedicated move instructions and can conditionally branch based on the FPU status.
The FPU has 32x32-bit F-Regs (FPU working registers) for single-precision operations. If using double-precision operations, the FPU utilizes the existing F-Regs to allow for 16x64-bit F-Regs. It also has seven alternate contexts for F0-F7 in addition to alternate contexts for FCR and FSR:
Instruction Set
ISA Classification
dsPIC33A implements a hybrid Instruction Set Architecture (ISA), supporting both Register-Memory and Register-Register operations as shown:
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Additionally, the 72-bit Digital Signal Processor (DSP) Arithmetic Logic Unit (ALU) implements an Accumulator-Memory architecture, whereby one operand is implicitly the Accumulator (A or B).
Data Types
The CPU ALU in dsPIC33A supports arithmetic operations on three fundamental integer data types:
- 8-bit two's complement integers
- 16-bit two's complement integers
- 32-bit two's complement integers
The DSP ALU supports additional DSP fractional data types:
- Q15 (1.15) - 1-bit sign, 15 bits fraction
- Q31 (1.31) - 1-bit sign, 31 bits fraction
- Q31 (9.31) - 9-bit signed integer, 31 bits fraction
Additionally, the dsPIC33A devices feature a 33-bit-by-33-bit integer multiplier shared by both the MCU ALU and the DSP engine. The multiplier is capable of signed, unsigned, or mixed-sign operation and supports either 9.31 fractional (Q.31) or 64-bit integer results.
The FPU co-processor supports arithmetic operations on two fundamental floating point data types:
- Single-precision (IEEE 754-2019)
- Double-precision (IEEE 754-2019)
Instruction Categories
The dsPIC33A instruction set provides a rich suite of instructions that support traditional microcontroller applications and a class of instructions that support math-intensive applications. The majority of the instructions are encoded in a single 32-bit word and executed in a single instruction cycle.
The instruction set can be grouped into the functional categories shown in the accompanying table.
Many assembly language instructions can operate on byte (8-bit), word (16-bit) and long-word (32-bit) operands.
- Byte operations are indicated by appending a ".b" suffix to the instruction mnemonic, i.e., ADD.b
- Word operations are indicated by appending a ".w" suffix to the instruction mnemonic, i.e., ADD.w
- Long-word operations are indicated by appending a ".l" suffix to the instruction mnemonic, i.e., ADD.l
The instruction set is fully documented in the "dsPIC33A Programmer's Reference Manual."
Addressing Modes
The dsPIC33A supports two native Addressing modes for accessing data memory, along with several forms of immediate addressing. Data accesses may be performed using file register addressing, indirect addressing, and immediate addressing, allowing a fixed value to be used by the instruction. The data memory address range accessed by each Addressing mode is summarized in the accompanying table.
Please review the "dsPIC33A Programmer's Reference Manual" for data addressing mode examples.