Oscillator Module Interrupts

Last modified by Microchip on 2026/10/19 09:36

The oscillator-related interrupt and fault detection features in the dsPIC33A clock system work together to improve clock reliability, functional safety and system robustness.

Overview

Interrupt and fault detection features include:

Clock Monitor (CM) interrupts and status events
Fail-Safe Clock Monitor (FSCM) fault handling
Clock Selection Integrity Check and error detection

interrupts overview

Let's review these features.

Clock Monitor Event Interrupts

When enabled, the Clock Monitor generates interrupts for Count Ready, Saturation, Warning, and Clock Failure events.

Clock Monitor Interrupt Vectors and Interrupt Service Routines (ISRs)

Each Clock Monitor event has its own dedicated interrupt vector and Interrupt Service Routine (ISR), allowing software to respond independently to different clock conditions.

There are specific and individual interrupt flags for each interrupt source:

Interrupt Vectors & ISRs	Interrupt Flags
Clock Monitor Count Ready void __attribute__((interrupt)) _CMxCNTInterrupt(void)	CMxCNTIF
Clock Monitor Saturation void __attribute__((interrupt)) _CMxSATInterrupt(void)	CMxSATIF
Clock Monitor Clock Warning void __attribute__((interrupt)) _CMxWARNInterrupt(void)	CMxWARNIF
Clock Monitor Clock Fail void __attribute__((interrupt)) _CMxFAILInterrupt(void)	CMxFAILIF

The Clock Monitor Module supports up to four monitor channels, where x = 1 through 4.

In total, the device provides 16 dedicated Clock Monitor interrupt vectors for detailed clock monitoring and fault handling.

Clock Monitor Event Status Bits

The Clock Monitor Status Register (CMxSTAT) provides status information for Clock Monitor events and threshold conditions. These status bits allow software to quickly identify clock warnings, failures, and measurement events.

Clock Monitor Event Interrupt SFRs and Bits

The Clock Monitor Module provides 16 dedicated interrupt flags in the IFS0 register for Count Ready, Saturation, Warning, and Fail events across the four Clock Monitor channels.
The IEC0 register contains the corresponding interrupt enable bits, allowing each Clock Monitor interrupt source to be individually enabled or disabled by software.
Interrupt priority levels are configured using the IPC1, IPC2 and IPC3 registers, with each Clock Monitor interrupt assigned its own programmable priority group.

FSCM Interrupts

When enabled, the FSCM generates a shared interrupt when a Clock Generator or Phase-Locked Loop (PLL) failure is detected.

FSCM interrupts

FSCM Interrupt

All Clock and PLL detected fails share one interrupt vector and ISR:

void __attribute__((interrupt)) _CLKFInterrupt(void)

Inside the shared ISR, software checks the Clock Failure (CLKFAIL) status register to determine which specific clock or PLL caused the failure:

Clock fail status bit:

```
CLKFAILbits.CLKxFAIL (x = 1 - 14)
```

PLL fail status bit:

```
CLKFAILbits.PLLxFAIL (x = 1 or 2) 
```

When CLKxFAIL or PLLxFAIL == 1, Failure detected

When CLKxFAIL or PLLxFAIL == 0, No failure detected

By the time the FSCM interrupt occurs:

The system has already switched to the backup clock source
OSWEN = 0 indicates the clock switch is complete

FSCM Interrupt SFRs and Bits

FSCM Interrupt SFRs and bits

The FSCM interrupt uses the Clock Failure Interrupt Flag (CLKFAILIF) to indicate when a Clock Generator or PLL failure has occurred.

The Clock Failure Interrupt Enable (CLKFAILIE) bit enables or disables the FSCM interrupt, allowing software control of clock-fail event handling.

Interrupt priority is configured using the CLKFAILIP[2:0] bits, with the default POR priority level set to 4.

Clock Selection Integrity Check Interrupts

Clock Selection Integrity Check generates an interrupt if an unintended or unsafe clock switch is detected while a clock source is active.

All clock selection integrity events share a single interrupt vector for centralized fault handling.

Clock Selection Integrity Check Interrupt

All clock and PLL integrity clock errors share one interrupt vector and ISR:

void __attribute__((interrupt)) _CLKEInterrupt(void)

Inside the shared ISR, software checks the System Clock Selection Failure (SCSFAIL) status register to check which specific clock or PLL caused the error:

Integrity check clock fail status bit:

```
SCSFAILbits.CLKxSCS (x = 1 - 14)
```

Integrity check PLL fail status bit:

```
SCSFAILbits.PLLxSCSL (x = 1 or 2) 
```

When CLKxSCS or PLLxSCS == 1, Integrity error detected

When CLKxSCS or PLLxSCS == 0, No integrity error detected

Clock Selection Integrity Check Interrupt SFRs and Bits

Here we see three main points:

The Clock Error Interrupt Flag (CLKERRIF) indicates when a Clock Selection Integrity Check interrupt has occurred.
The Clock Error Interrupt Enable (CLKERRIE) bit enables or disables Clock Integrity Check interrupts.
Interrupt priority is configured using the CLKERRIP[2:0] bits, with priority level 4 as the default POR setting.