Power-Saving Modes
The PWRSAV instruction that initiates Idle and Sleep modes is primarily responsible for reducing processor and system power consumption.
The Oscillator module supports multiple Sleep and Idle modes for power reduction:
- Idle mode keeps clocks running while the CPU is halted, providing a fast, low‑latency return to execution.
- Sleep mode delivers the lowest power consumption by stopping the system clock, halting the CPU and most peripherals.
For Clock Generator 1 (CLKGEN 1):
- Idle mode: System clock stops, peripheral clock, peripheral clock divided run
- Sleep mode: System clock, peripheral clock, peripheral clock divided stop
Other clock and Phase-Locked Loop (PLL) generators:
- Stop in Idle: CLKGENx/PLLx stop in Idle
- Run in Sleep: CLKGENx/PLLx run in Sleep
The Stop in Idle (SIDL) and Run In Sleep (RIS) options are user selectable via the SIDLE and RIS bits in the CLKxCON/PLLCONx registers.
If the SIDLE bit is set in a CLKxCON/PLLCONx register, the associated clock will stop if CPU IDLE is asserted.
The SIDLE bit has no effect if CPU Sleep is asserted. If the RIS bit is set in a CLKxCON/PLLCONx register, the associated clock will continue to run even if CPU Sleep is asserted. The RIS bit has no effect if CPU Idle is asserted.
A selected peripheral can operate during Sleep if it uses an active clock source, such as the Fast RC Oscillator (FRC).
The peripheral interrupt can wake the device from Sleep, allowing continued operation to service the interrupt.