Main Core intended for communications and supervisory control
Secondary Core intended for time-critical control applications such as SMPS or motor control
Each core has its own peripheral set
Inter-core communications through low-latency mailboxes
Configurable cross-core fault and interrupt signals
Reconfigurable pins through Microchip's Peripheral Pin Select
Programming Considerations
An application is written for each core. Both applications are combined by the IDE into one HEX file and programmed into the device's flash program memory. At start-up, before the user application runs, the compiler-inserted start-up code copies the secondary application from the program flash to the high-speed PRAM for execution by the Secondary Core.
If you need to work with Microchip Support staff directly, you can submit a technical support case. Keep in mind that many questions can be answered through our self-help resources, so this may not be your speediest option.
