Audio-Tone Generation Using a Lookup Table With MPLAB® Harmony v3: Step 3

Last modified by Microchip on 2023/11/09 09:07

Verify Configuration Bits are Correct

Click on the System block in the Project Graph window to view the System Device & Project Configuration options.

System Device and Project Configuration options

Expand the Device & Project Configuration and PIC32MZ2048EFH144 Device Configuration selection tree to view the PIC32 core configuration selections. The BSP you selected has properly configured these selections for you. This step shows you how to make changes to these selections if needed.

  • DEVCFG3 and DEVCFG2: No change required.
  • DEVCFG1: Verify Watchdog Timer Enable (FWDTEN) is OFF.
  • DEVCFG0: Verify Debugger Communication Channel (ICESEL) is set to ICS_PGx2.

In case you are wondering where these cryptic selection names come from, they correspond to the PIC32 core configuration registers and bit names.

Also, be sure to set the Use Cache Maintenance block under MIPS Configuration > CACHE.

Open Cache from the MIPS Configuration option

The above configuration is enabled to generate the cache maintenance API. The cache maintenance APIs are used in this application to address the cache coherency issues observed in transferring the data using DMA.

In the same system configuration window, expand the DMA (DMAC) tree options. Enable Channel 0 (for SPI1_TX) and Channel 1 (for SPI_RX).

DMA (DMAC) Tree Options

DMA channels need to be configured for the audio I²S component driver's use. DMA Channel 0 is used to transmit and DMA Channel 1 is used to receive.

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