Audio-Tone Generation Using a Lookup Table With MPLAB® Harmony v3: Step 4

Last modified by Microchip on 2023/11/09 09:07

Verify and Change Oscillator Settings

Select the Clock Diagram tab to display the Clock Configurator window.

You can open the MPLAB® Harmony Configurator (MHC) Clock Configurator window by clicking on MHC > Tools > Clock Configuration.

  • Verify the BSP has correctly configured the following clock parameters for you:
    • POSCMOD set to EC.
    • FNOSC set to SPLL.
    • FPLLIDIV set to DIV_2.
    • FPLLMULT set to MUL_33.
    • FPLLODIV set to DIV_2.
    • FPLLRNG set to 8-16 Mhz.

Clock Block Diagram

Experiment with other clock settings. Did you notice how some selections produce red values? These indicate a bad clock configuration. If you hover over them, a pop-up window will explain the problem.

The PIC32 is connected to a 24 MHz external clock input. You are not using the internal PIC32 oscillator.

When you change the configured clocks away from the default values on the graphical interface, the corresponding selections in the Options tab highlight these changes with a light green background. Any dependency changes made by the system will be highlighted with a light purple background. All selections made under the Clock Diagram tab are reflected under the Options tab. The reverse is also true. You can configure the clocks using the tree selections, but it is much easier to do that graphically.

Clock Block Diagram

Configuration Options tab

For custom boards without a BSP, you can use the Phase-Locked Loop's (PLL’s) Auto Calculate feature to determine and set the PLL to multiply and divide values (FPLLIDIV, FPLLMULT, and FPLLODIV). You can see how this works by going back to the Clock Configurator window (Clock Diagram tab).

Change the PIC32 clock frequency to 198 MHz.

This development board can run at a maximum frequency of 200 MHz (selected by default by the BSP). You are using the audio codec on the board, so you need to configure the system frequency to 198 MHz. This change will be explained when you configure the reference clock to provide the MCKI to the audio codec.

  • In the MHC Clock Diagram tab, find the System PLL block and select Auto Calculate.
  • Change the Desired System Frequency from 200 MHz to 198 MHz.
  • Select Apply.

Verify the output to the PLL is now set to 198 MHz.

MHC Clock Diagram tab

When you click on a block in the MHC Project Graph tab, the Configuration Options window will show various options you can choose. You can reference information about the device’s configuration settings in the compiler’s user guide and in the device’s datasheet. If your hardware and debugger connections are correct and you are unable to program, debug, or run code on the device, it is very likely that one of these key device configuration settings is incorrect. Before continuing, you must ensure that these settings are correct.