Low-Power Application on SAM D21 Using MPLAB® Harmony v3 Peripheral Libraries: Step 1
Create MPLAB® Harmony v3 Project Using MPLAB® X IDE.
Figure 1
In the Categories pane of the New Project dialog window, select Microchip Embedded. In the Projects pane, select Application Project, then click Next.
Figure 2
Enter the Device name as follows:
Device: Select ATSAMD21J18A as the target device.
After selecting the target device, click Next to select the compiler.
Figure 3
In the Select Compiler window, select the Compiler version in the Compiler toolchains pane, expand the XC32 section, and select XC32 (v4.45) [C:\Program Files\Microchip\xc32\v4.45\bin].
Click Next to proceed to Select Project Name and Folder.
Figure 4
In the Select Project Name and Folder window, apply the following settings:
- Project Name: Indicates the name of the project that will be shown in MPLAB X IDE. Enter "low_power_samd21_xpro" to set the project's name.
- Project Location: Indicates the path to the root folder of the new project. All project files will be placed inside this folder. The project location can be any valid path, for example: C:\mchp_harmony_v3\dev\samd21_low_power\firmware
Figure 5
After selecting the Project Name and Folder, click Finish to launch MPLAB Code Configurator (MCC).
The MCC plugin’s main window for the project will be displayed as shown in Figure 6.
Figure 6
Configure Clock Settings
Launch Clock Easy View by going to the Project Graph tab in MPLAB X IDE and then selecting Plugins > Clock Configuration.
Figure 7
A new window, Clock Easy View, will open.
The Clock Easy View window displays a default CPU clock set to 47,972,352 Hz.
Figure 8
Enable and configure the 32K Crystal Oscillator. Click on the Settings (wheel) button and enable the Run Oscillator in Standby Sleep Mode.
Figure 9
Figure 10
Enable GCLK2 with the clock source set to XOSC32K. Click on the Settings (wheel) button and enable the Run GCLK2 in Standby Sleep Mode.
Figure 11
Figure 12
Enable and configure the Digital Frequency Locked Loop (DFLL).
Figure 13
Check the CPU clock. Now CPU clock is set to 47,972,352 Hz as the DFLL configuration changed.
Figure 14
Enable GCLK1 with the clock source set to OSCULP32K. Set the GCLK1 output frequency as 1 kHz by configuring the division factor with 32. Click on the Settings (wheel) button and check the box for GCLK should keep running in Standby mode.
Figure 15
Figure 16