PLD Hardware Tools

Last modified by Microchip on 2024/01/11 21:53

Industry Standard Programmer Kits


This development/programmer kit supports the ATF15xxAS/ASL/ASV/ASVL family of 3.3V and 5.0V industry-standard, pin-compatible CPLDs with Logic Doubling. This kit includes an ATDH1150USB USB-based ISP cable, a 44-TQFP adapter module, and ATF15xxAS/ASV samples in 44-pin TQFP packages. Adapter modules that support the 44-pin PLCC, 84-pin PLCC, and 100-pin TQFP packages are available separately. The 44-pin TQFP adapter module can also be purchased separately.


The ATF15xx CPLD USB-based JTAG ISP Download Cable connects to a standard USB port on a PC and to a 10-pin or 14-pin JTAG header on the programming circuit board. It transfers the JTAG instructions and data generated by the ATMISP software running on a PC to the ATF15xx series of CPLDs on the target circuit board. With this In-System Programming (ISP) download cable, you can easily download design changes directly to the ATF15xx JTAG devices for easy prototyping of your designs.

Software Tools


  • WinCUPL

    • WinCUPL is a complete, easy-to-use, Windows® OS-based design software for all Microchip SPLDs and CPLDs. It supports CUPL design entry and functional simulation and includes the latest fitter technologies.


  • ProChip Designer®

    • ProChip Designer is a full-featured EDA suite with state-of-the-art Mentor Graphics (Precision Synthesis RTL for Verilog and VHDL) tools integrated into a user-friendly design environment. This suite also includes a JTAG in-system programming utility and fitter technologies to enable logic doubling in ATF15xx CPLDs. Optional add-on tools support schematic and CUPL design flows. Precision Synthesis RTL tool requires an approved license. 

    • POF2JED is a Windows OS-based software tool that converts Altera POF files to JEDEC files for the ATF15xx CPLDs. It supports all packages and speed types for the ATF1500/A, ATF1502AS/ASV, ATF1504AS/ASV, and ATF1508AS/ASV devices.
    • POF-to-JEDEC File Conversion Utility Version 4.45.1
    • To install, unzip this file into a TEMP folder and double-click on the POF2JED_Setup.exe file.
  • BSDL Files

    • These Boundary Scan Description Language (BSDL) files are for the ATF1502, ATF1504, and ATF1508 CPLDs with IEEE® Standard 1149.1 JTAG support.

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