Skip to Content

Hello FPGA

5th Generation Architecture

Last modified by Microchip on 2025/01/31 12:58
   4th Generation Architecture  Microchip FPGA Applications   

Introduction

Let's explore the PolarFire® Field Programmable Gate Arrays (FPGAs) and PolarFire System-on-Chip (SoC) mid-range families together. These families are built on the 5th-generation FPGA architecture and are crafted using a 28-nanometer process.

PolarFire® FPGA Architecture

Figure1 shows the block diagram of the PolarFire FPGA architecture. Your PolarFire FPGA transceiver block has four lanes, supporting data rates ranging from 250 megabits per second to 12.7 gigabits per second. Depending on the model, you may have between one and six transceiver blocks, allowing for up to 24 lanes. The transceiver features a PIPE mode for soft PCI Express® (PCIe®), an 8B10B encoder and decoder, and a 64B66B mode for encoding and decoding.

The transceiver has a built-in Pseudo-Random Bit Stream (PRBS) generator and checker to facilitate link testing and diagnostics, as well as an eye monitor to visualize the eye diagram at the receiver. Each member of the PolarFire family includes one transceiver with two embedded PCIe subsystem blocks, capable of supporting Gen 2 root port and endpoint topologies. Some models feature additional transceiver blocks without the PCIe subsystem blocks.

The FPGA fabric has up to 487,000 logic elements and as many as 1,480 math blocks for Digital Signal Processing (DSP) operations. The logic element includes an input Look-Up Table (LUT) and D flip-flop, similar to those found in IGLOO® 2 FPGAs. With up to 33 megabits of Static Random Access Memory (SRAM), you'd have access to two types of SRAM blocks:

  1. A micro SRAM block of 768 bits with two ports, and
  2. A larger 20-kilobit SRAM block capable of implementing two-port or dual-port RAM, complete with optional error detection and correction to handle two-bit errors and correct one-bit errors.

Soft IP functions are available to support serial interface protocols like JESD204B, Interlaken, and Serial Advanced Technology Attachment (SATA). Soft processor cores based on the Reduced Instruction Set Computer, version five (RISC-V) architecture are also available. You can work with up to 584 inputs/outputs (I/Os), organized into banks. The High-Speed I/O (HSIO) bank includes built-in I/O gearing logic, supporting Double Data Rate (DDR) memories of up to 1600 megabits per second, while your General-Purpose I/O (GPIO) bank, also with built-in I/O gearing logic and clock data recovery, operates at speeds of up to 1600 megabits per second and supports high-speed serial protocols such as serial Gigabit Ethernet.

The system controller manages device programming, design, security, and key management, authenticating and decrypting the incoming bitstream to initiate programming. The PolarFire FPGAs come with several built-in tamper detection features, including monitors for voltage, frequency, and temperature. PolarFire SoC devices add a dedicated user Crypto Co-processor to your arsenal for data security applications designed to resist side-channel attacks like Differential Power Analysis (DPA).

PolarFire FPGA Architecture Diagram

Figure 1: PolarFire® FPGA Architecture

Back to Top

PolarFire SoC Architecture

Figure 2 shows the block diagram of the PolarFire SoC architecture. The transceiver blocks and FPGA fabric are identical to the standard PolarFire devices. The SoC variant enhances the capabilities with a hard microcontroller subsystem, featuring a 64-bit multicore RISC-V processor cluster to support both Linux® and real-time applications. This processor subsystem includes one RISC-V monitor core and four RISC-V Linux-capable application cores, each with physical memory protection.

The PolarFire SoC also includes a flexible, two MB L2 memory subsystem that serves as an L2 cache or scratchpad memory with a deterministic mode for real-time applications. The integrated DDR controller within the microcontroller subsystem supports various memory types, including DDR3, DDR4, LPDDR3, and LPDDR4, alongside 128 kilobytes of boot flash memory with error detection and correction across all microcontroller subsystem memories.

Performance monitors in your PolarFire SoC can be activated based on transaction events, featuring 240-bit event counting, control status registers, and two event selector control status registers. An instruction trace block helps identify performance and fault points during program execution, and dynamic Advanced eXtensible Interface (AXI) bus monitors allow you to oversee traffic over an AXI bus.

For debugging, your PolarFire SoC supports up to 50 hardware breakpoints or watchpoints. The microcontroller subsystem peripherals include:

  • An Athena TeraFire® Crypto Co-processor for data security applications
  • Two Gigabit Ethernet Media Access Controllers (MACs)
  • A Multi-Media Card (MMC) 5.1 controller compatible with Secure Digital (SD) and Secure Digital Input Output (SDIO) memory cards
  • Two Controller Area Network (CAN) controllers
  • An execute-in-place quad Serial Peripheral Interface (SPI) flash controller, enabling the system to boot directly from SPI flash

Additionally, it has:

  • Two SPI controllers
  • Two I2C interfaces
  • Five multi-mode Universal Asynchronous Receiver/Transmitters (UARTs)
  • 32 individually configurable general-purpose I/Os
  • A real-time counter
  • One USB 2.0 On-The-Go controller at your command
PolarFire SOC architecture

Figure 2: PolarFire® SoC Architecture

You can also find this course in video format from Microchip University as "Hello FPGA".

Back to Top