Hello FPGA

4th Generation Architecture

Last modified by Microchip on 2025/01/29 17:10

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Introduction

We will now explore the SmartFusion® 2 and IGLOO® 2 Field Programmable Gate Arrays (FPGAs) low-density families. SmartFusion 2 and IGLOO 2 FPGAs are based on the 4th generation FPGA architecture and are fabricated at 65 nanometers. Both SmartFusion 2 and IGLOO 2 FPGAs feature the Flash*Freeze low-power mode found in IGLOO FPGAs.

IGLOO 2 FPGA Architecture

The logic element consists of:

  • Four-input Lookup Table (LUT)
  • D flip-flop

Depending on the family member, you'll find anywhere from 6,000 to 150,000 logic elements.

The FPGA fabric includes:

  • Math blocks for Digital Signal Processing (DSP) operations
  • A small Random Access Memory (RAM) block of 1152 bits
  • A large Static Random-Access Memory (SRAM) block of 18K bits. You can concatenate SRAM blocks to create larger memories.

At the top of Figure 1 is the high-performance memory subsystem.

This subsystem includes:

  • 128K, 256K, or 512K bytes of embedded flash memory
  • 64K bytes of embedded SRAM
  • A hard 667 megabit per second Double Data Rate (DDR) memory controller that supports DDR2, DDR3, and LPDDR memories. All of the memories in the high-performance memory subsystem come with optional error detection and correction.

There is a Serial Peripheral Interface (SPI) controller for programming and two Direct Memory Access (DMA) engines for data movement. The Peripheral DMA (PDMA) transfers data between peripherals or fabric SRAM and the High-Performance Memory Subsystem (HPMS)-embedded SRAM. The High-Performance DMA (HPDMA) moves data between IGLOO 2 RAM blocks and DDR memory.

The system controller is depicted on the left of the diagram. It authenticates and decrypts incoming bitstreams, manages programming and verification, and handles other operations such as initiating the Flash*Freeze mode. The system controller also includes several cryptographic hardware accelerators for data security applications.

The high-speed serial interface blocks are at the bottom of the diagram. Each high-speed serial interface block has four lanes and supports data rates from 1 Gbps to 5 Gbps. It's compatible with PCI Express® (PCIe®) Gen 2 endpoint topology,  10 Gigabit Attachment Unit Interface (XAUI), and user-defined high-speed protocols such as 1000Base-X and JESD204B. In the IGLOO 2 family, you can have up to four high-speed serial interface blocks, totaling 24 lanes.

Igloo2 Architecture Diagram

Figure 1: IGLOO 2 FPGA Architecture

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SmartFusion 2 FPGA Architecture

SmartFusion 2 is a System-on-Chip (SoC) FPGA, shown in Figure 2, which builds upon IGLOO 2 by adding a hard microcontroller subsystem. This includes a 166 MHz Arm® Cortex®-M3 microcontroller with an 8K byte instruction cache and peripherals. The SmartFusion 2 microcontroller subsystem incorporates the embedded SRAM, embedded flash memory, and the DDR controller found in IGLOO 2.

Each SmartFusion 2 device comes with:

  • One triple-speed Ethernet Media Access Control (MAC)
  • One Controller Area Network (CAN) controller
  • One Universal Serial Bus On-The-Go (USB OTG) controller
  • Two timers
  • Two SPI controllers
  • Two Universal Asynchronous Receiver-Transmitters (UARTs)
  • Two I2C blocks

There's also a watchdog timer to prevent system crashes and a real-time calendar for clock functionality.

Finally, SmartFusion 2 includes both the PDMA controller and HPDMA controller found in IGLOO 2.

SmartFusion Architecure Diagram

Figure 2: SmartFusion 2 FPGA Architecture

This course is also available in video format from Microchip University: Hello FPGA.

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