Design Flow

FPGA Design Flow

Design flow starts with a design capture, as illustrated in the Figure 1 flowchart.  You would typically use a Hardware Description Language (HDL) to describe your designs. You simulate the HDL description to verify that the functionality is correct. The synthesis step converts your HDL description into a structural netlist targeting a specific FPGA family.

Place and route assign the gates in your structural netlist to a location on the FPGA die and make connections. Timing and power verification confirm that your design objectives are met. Post-layout simulation can be used to verify that the timing requirements are met. After verifying timing and power requirements, you program the FPGA.

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Capture Design

Describe Behavior using HDL

Your FPGA designs are typically implemented using HDL such as Very High-Speed Integrated Circuit Hardware Description Language (VHDL), Verilog®, and SystemVerilog to describe the system's behavior.

Simulate HDL Descriptions

You can simulate and synthesize HDL descriptions to produce a netlist containing gates for the target FPGA family.

Block base Approach

Some of your designs may be captured using a block-based approach with vendor-specific intellectual property, cores, and tools.

Example 1

Figure 2 shows an example of a description of a four-input AND gate in VHDL and Verilog. In the VHDL description, you would write "Q is assigned A and B and C and D". In the Verilog description, you would write "assign Q = A & B & C & D". This way, you are describing the behavior of a four-input AND gate.

Example 2

Figure 3 presents a second example: a 16-bit multiplier written in VHDL and Verilog. In the VHDL description, you would write "Q is assigned A * B". In Verilog, you would write "assign Q = A * B". This describes the behavior of your circuit without instantiating any gates to implement your multiplier.

Using an HDL description makes your designs portable because the same description can be used to target different technologies. It's also easy to make modifications, such as changing the port width from 16-bits to 32-bits. 

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Synthesis

The synthesis step converts your HDL description to logic gates.

Figure 4 exhibits your description of a 16-bit multiplier in Verilog. After synthesis, you would have a netlist containing gates from the target FPGA family, in this case, PolarFire^®.

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Place and Route

The place and route step takes the cells in the netlist from synthesis, places them on the FPGA die, and makes the interconnects. When it's finished, it calculates the timing information based on the placement of the logic. The cells in the structural netlist are placed on the FPGA die. Figure 5 displays a PolarFire FPGA die; the dark blue boxes are locations where logic has been assigned.

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Simulate

You might simulate at various stages in the FPGA design flow. You can simulate the HDL description during design capture to confirm that the description matches the design's functional specifications. After running place and route, you can simulate to confirm that the design meets the timing specifications.

There are many simulators available. Some of the popular simulators are:

• ModelSim^®
• Questa^® SIM
• Active-HDL™
• Riviera-PRO™

Figure 6 showcases functional simulation for your four-input AND gate example. You're looking at the wave window from the simulator, and you can see the four inputs A, B, C, and D, and your output Q. The output Q goes high when all of the inputs are one and goes low when one or more inputs go low. This confirms that your Verilog description matches the functionality of a four-input AND gate.

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Programming

Programming configures the FPGA. SRAM-based FPGAs typically need an external flash memory device to hold the bitstream. When the board is powered, the flash memory is read, and the FPGA is configured (represented by the upper image in Figure 7), where the microchip holds the flash memory and is sent to the SRAM FPGA via SPI.

Microchip's flash-based FPGAs have a non-volatile programming element directly programmed, so external flash memory is not required (as shown in the lower part of Figure 7).

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Additional Resources

​This course is also available in video format at Microchip University as Hello FPGA.​

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