Hello FPGA
How to Choose the Right FPGA
Microchip FPGA Applications | Design Flow |
Introduction
Some criteria for you to consider when choosing the appropriate Field Programmable Gate Array (FPGA) family for your next design include:
- The number and type of I/O required
- The number of logic elements in the design
- The amount and type of RAM needed
- Any hard IP blocks required
Number of I/O
Total I/O Count
The number of I/Os is probably the easiest to estimate. Add up the number of inputs and outputs in the design.
I/O Standards Required
Make sure to consider the type of I/Os that are required for the application. This includes single-ended standards like LVTTL and LVCMOS, differential standards like LVDS, and voltage reference standards like SSTL to interface with high-speed memories.
Specific I/O Features
Also, consider specific I/O features needed, such as Schmitt trigger inputs or hot-swapping capability to allow a board to be plugged into a powered rack without disturbing the data buses.
Figure 1 charts the I/O count for Microchip Complex Programmable Logic Device (CPLD) replacement families. The IGLOO® nano and ProASIC® 3 nano families are available with 23 to 71 I/Os in very small packages. The IGLOO PLUS family members have between 101 and 112 I/Os.
For higher pin counts, you might consider ProASIC 3L, ProASIC 3, or IGLOO nano. These families have devices with a maximum of 341 to 620 I/Os. The larger members of the ProASIC 3L, ProASIC 3, and IGLOO families have I/Os that support differential I/O standards and voltage reference I/O standards for interfacing with high-speed memories.

Figure 1: CPLD Replacements - Total I/O
The chart in Figure 2 depicts the I/O count for Microchip's mid-range and low-density FPGA families. The PolarFire® FPGA family has between 170 and 584 I/Os. SmartFusion® 2 and IGLOO 2 FPGA families have between 84 and 574 I/Os. Both families support differential I/O standards and voltage reference I/O standards.

Figure 2: Mid-Range and Low-Density FPGAs Total I/O
Number of Logic Elements
Estimating the number of flip-flops in your design is a good way to get an early estimate of the number of logic elements required. To estimate the number of flip-flops in your design, take the number of counter bits, add the number of bits for any registers in your design—such as shift registers, control, and status registers, or register files—and add the number of flip-flops for any state machines in your design. A conservative estimate for state machines is to assume one hot encoding is used, where there is one flip-flop per state. The sum is the total number of flip-flops you need. See the calculation in Figure 3.

Figure 3: Total Flip-Flop Calculation
Figure 4 shows the number of flip-flops that are available in the Microchip CPLD replacement families. The IGLOO PLUS, IGLOO nano, and ProASIC 3 nano families have between 1,000 and 3,000 flip-flops. The ProASIC 3L, ProASIC 3, and IGLOO families have members with up to 35,000 flip-flops.

Figure 4: Flip-Flop Estimation
For higher-density designs, you might consider the Microchip low-density or mid-range families. The SmartFusion 2 and IGLOO 2 FPGA low-density families have between 6,000 and 146,000 flip-flops. The PolarFire mid-range FPGA family has between 109,000 and 481,000 flip-flops. The comparison can be seen in Figure 5.

Figure 5: SmartFusion 2 and Igloo 2 FPGA Flip-Flop Count
RAM Requirements
If your design requires RAM, you'll need to estimate the total amount of RAM required and the type of RAM, such as two-port, dual-port, or FIFO. Also, consider if your design requires flash memory or read-only memory. Finally, consider any specific RAM features you need, such as built-in error detection and correction. You can use the RAM configurator in the Libero® SoC Design Suite software to build blocks of RAM to help with the estimate.
The IGLOO nano, ProASIC 3 nano, and IGLOO PLUS families have between 18 Kb and 36 Kb of RAM and are a good choice for a CPLD replacement if a small amount of RAM is needed. The ProASIC 3L, ProASIC 3, and IGLOO families have up to 504 Kb of RAM. See the RAM comparison chart in Figure 6.

Figure 6: RAM Requirements
The mid-range PolarFire FPGA family has between 7.6 Mb and 33 Mb of RAM. The PolarFire FPGA large SRAM blocks have built-in error detection and correction.
The SmartFusion 2 and IGLOO 2 FPGA low-density families have between 703 Kb and 5 Mb of RAM. Figure 7 compares of the number of flip-flops in the mid-range and low-density FPGAs.

Figure 7: Flip-Flop Count Comparison
Hard IP Blocks
Consider whether your design requires any hard IP blocks, such as:
- Math blocks for Digital Signal Processors (DSPs) functions
- Embedded microprocessor and the type of processor desired
- Analog blocks such as analog-to-digital or digital-to-analog converters
- Transceivers for high-speed serial communication and the required speed.
- Memory controller to interface with Double Data Rate (DDR) memories such as DDR2, DDR3, or DDR4
Summary
Figure 7 provides the embedded features available in the CPLD replacement families. The IGLOO, ProASIC 3, and ProASIC 3L families have one or six Phase-Locked Loops (PLLs) for clock frequency synthesis. The smallest members of these families don't have a PLL. The IGLOO, ProASIC 3, and ProASIC 3L families don't have any other embedded features.
The SmartFusion SoC FPGA family has one or two PLLs, a hard external memory controller that supports synchronous SRAM, pseudo-static SRAM (PSRAM), and NOR flash memories, a 100 MHz Arm® Cortex®-M3 microcontroller and peripherals, and analog blocks containing two or three analog-to-digital and digital-to-analog converters.

Figure 8: CPLD Replacement Features
Figure 9 summarizes the embedded features in the low-density and mid-range families. IGLOO 2 and SmartFusion 2 FPGA families have between 11 and 240 math blocks for implementing DSP functions, two to six or eight PLLs for clock frequency synthesis, and transceivers that operate between one gigabit per second and five gigabits per second with built-in PCI Express® 2.0 (PICe® Gen 2) endpoint support. Both families have a hard external memory controller that supports DDR2, DDR3, and LPDDR memories. Soft processors based on the RISC-V instruction set are available for IGLOO 2 FPGAs. SmartFusion 2 FPGAs includes a hard 166 MHz Arm Cortex-M3 microcontroller and peripherals.
PolarFire has between 336 and 1,480 math blocks, eight PLLs, and eight DLLs for clock frequency synthesis and phase adjustments, and transceivers that operate between 250 megabits per second and 12.7 gigabits per second with built-in PICe Gen 2 endpoint or root port support. A soft external memory controller that supports DDR4, DDR3, and LPDDR3 memories is available. Soft Arm Cortex-M1 or RISC-V cores are available for PolarFire devices.

Figure 9: Low Density and Mid-Range Features
Finally, consider if your design requires any other attributes, such as:
- Live at power-up: Is your design performing system management functions that can't wait for an FPGA to be configured?
- Low power: Is your design being deployed in packaging that would make it difficult to add a heat sink or a fan for cooling?
- Packaging: Is your design in a space-limited enclosure that requires small packaging?
These are some of the considerations that can help you select the correct FPGA for your design.
Video Course
You can also find this training in video format from Microchip University as "Hello FPGA".