Establishing Step Command Timing

Last modified by Microchip on 2023/11/09 09:00

When setting up the clock controlling the execution speed of the Peripheral Trigger Generator (PTG) Step commands, three parameters need to be considered:

  1. The signal used as the base clock source for the PTG module
  2. The number of clock periods needed for each Step command cycle (prescaler)
  3. Whether or not the sequence will need to extend the clock cycle (step delay timer)

Block Diagram for PTG Clock

Clock Source and Prescaler

The PTG Control Register (PTGCON) controls the clock source and the prescale value for the PTG module. There are six signals which can be set as the PTG clock. Once the clock has been determined, the application can divide the clock by a value between 1 and 32.

PTGCON: PTG Control Register

Bit Definitions for PTGCON Register

bit 15-13

PTGCLK<2:0>: Select PTG Module Clock

111 = Reserved
110 = Reserved
101 = Clock source will be T3CLK
100 = Clock source will be T2CLK
011 = Clock source will be T1CLK
010 = Clock source will be ADC FRC clock
001 = Clock source will be Fosc
000 = Clock source will be Fp

bit 12-8

PTGDIV<4:0>: PTG Clock module Prescaler (Divider) value

11111 = Divide by 32
11110 = Divide by 31
0001 = Divide by 2
0000 = Divide by 1

Selecting the PTG Clock and Prescaler Using the MPLAB® XC16 C Compiler

// include the XC header file to define all register and bit names
#include <xc.h>

//  Select Fosc as the clock, with prescaler of 10
PTGCLK = 1;         // clock source set to Fosc
PTGDIC = 0x09;      // set prescaler to 10

// Select FP as clock source with NO prescaler
PTGCLCK = 0 ;       // clock source set to Fp
PGTDIV = 0 ;        // set prescaler to 1

Delaying PTG Step Cycle

Using the PTG Step Delay Limit register (PTGSDLIM) causes the Step commands lot to execute at a slower rate than the period set by PTGCON. When enabled, PTGSDLIM acts as a second prescaler for the PTG module. The PTG clock will be divided by the value of PTGSDLIM. The use of the step delay timer is optional, as it can be enabled or disabled at runtime by using the PTGCTRL Step command.

  • PTGCTRL with <OPTION> = 0b0010 (2) disables the Step delay.
  • PTGCTRL with <OPTION> = 0b0110 (6) enables the Step delay.

// include the XC header file to define all register and bit names
#include <xc.h>

//  Load Step Delay Limit register
PTGSDLIM = 4;    

// Sample Step Queuse
_STEP0 =   PTGWHI | 0;  
_STEP1 =   PTGCTRL |  6;  // enable Step Delay
_STEP2 =   PTGWHI | 1;    // wait for external trigger
_STEP3 =   PTGIRQ | 0;    // genearate PTG interrupt request
_STEP4 =   PTGCTRL | 2;   // disable Step Delay
_STEP5  =  JMP | 0;       // go to Step0 (i.e. repeat loop)

Learn More