Beginner Lab 12: DMA Demonstration

Last modified by Microchip on 2026/06/29 11:00

Objective

  1. Demonstrate and compare data transfer operations with and without CPU intervention by performing memory-to-memory transfers using both Direct Memory Access (DMA) and non-DMA (CPU-driven) methods on the PIC32CM LS00 Curiosity Nano+ Touch Evaluation Kit.
  2. Measure and compare the number of transfer cycles required for each method using the SysTick timer, emphasizing the performance advantages of DMA-based transfers.
  3. Transmit transfer status and cycle count information to a serial console via SERCOM Universal Asynchronous Receiver/Transmitter (UART).
  4. Implement and analyze the application using MPLAB® X IDE.

Overview

This lab exercise demonstrates the effectiveness of DMA in enhancing data transfer efficiency within embedded systems, using the PIC32CM LS00 Curiosity Nano+ Touch Evaluation Kit. The application is developed and tested in MPLAB X IDE.

Two memory-to-memory data transfer methods are implemented and evaluated:

  1. CPU-driven transfer (without DMA): The CPU actively copies data between memory locations.
  2. DMA-driven transfer (without CPU intervention): The DMA controller autonomously performs the data transfer.

Lab Activities

  • Configure the DMA controller by setting the source address, destination address, transfer size, and enabling the DMA channel.
  • Set up the SysTick timer in the project to function as a transfer cycle counter. Initialize the SysTick counter before starting the memory transfer. Read the cycle count after the transfer completes.
  •  Configure SERCOM UART for serial communication to print transfer status messages and transfer cycle counts to the console. Verify correct UART operation by observing the output on the serial terminal.
  • Implement application code to perform memory-to-memory data transfers both with and without DMA, allowing observation of CPU intervention.
  • Observe and compare the UART console outputs from both methods. Analyze the differences in transfer cycles for DMA and non-DMA transfers, confirming that DMA-based transfers complete in fewer cycles and operate more efficiently.

Expected Outcomes

Upon completing this lab, you will be able to:

  • Configure and initialize the DMA controller by correctly setting the source address, destination address, transfer size and enabling the DMA channel for memory-to-memory data transfers.
  • Set up and use the SysTick timer as a transfer cycle counter to measure and compare the number of cycles consumed during data transfer operations.
  • Configure SERCOM UART for serial communication and verify its operation by observing transfer status messages and cycle count outputs on a serial console.
  • Develop and integrate application code to perform memory-to-memory data transfers both with and without DMA, demonstrating the impact of CPU intervention.
  • Observe, analyze, and compare UART console outputs from both transfer methods to evaluate performance differences.
  • Conclude that DMA-based data transfers require fewer transfer cycles and operate more efficiently than CPU-driven transfers, reinforcing the advantages of using DMA in embedded systems.

Lab Source Files and Solutions

This ZIP file contains the completed solution project for this lab. It also contains the source files needed to perform the lab as per the following step-by-step instructions (see the "Lab Index" section on this page).

Download the ZIP file for this lab.

Information

The contents of this ZIP file need to be placed in the following folder:

<Any directory of user's choice>/
(example Directory = C:/microchip/harmony/v3)

Note:

  1. The project location of an MPLAB Harmony v3 project is independent of the location of the MPLAB Harmony framework path (in other words, there is no requirement to create or place an MPLAB Harmony v3 project in a relative path under the Harmony v3 framework folder). The project can be created or placed in any directory of user's choice.
  2. The point above is true, as an MPLAB Harmony v3 project generates all the referenced source and header files and libraries (if any) under the project folder when created.

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