Get Acquainted With SAM E51 DMAC Events
Introduction
Modern embedded systems increasingly rely on event‑driven architectures to achieve low latency, high performance and low power consumption. Instead of waking the Central Processing Unit (CPU) for every data movement or control decision, peripherals can communicate directly using hardware signals called events.
In the SAM E51 family of microcontrollers from Microchip Technology, the Direct Memory Access Controller (DMAC) is tightly integrated with the Event System, allowing Direct Memory Access (DMA) transfers to be triggered, controlled and monitored without CPU intervention. This lesson introduces DMAC events, explains how event inputs and outputs work, and shows how event‑driven DMA improves efficiency, determinism and system scalability.
Event System Overview and Benefits
The Event System is an on‑chip hardware routing network that allows peripherals to send signals directly to other peripherals. These signals, called events, propagate with minimal latency and do not require CPU involvement.
When combined with the DMAC, the Event System enables hardware‑only data movement. A peripheral can signal the DMAC to start, pause, resume, or modify a transfer. Likewise, the DMAC can notify other peripherals when transfers reach meaningful milestones. This reduces interrupt load, lowers power consumption by allowing the CPU to remain in sleep modes, and ensures deterministic response times that are critical in real‑time systems.
DMAC Event Inputs: Controlling DMA With Events
DMAC event inputs allow external hardware events to influence DMA channel behavior. Event input handling is enabled per channel using the Channel Control B register (CHCTRLB.EVIE). Multiple event actions may be enabled simultaneously, and any incoming event can trigger all enabled actions.
The DMAC can respond to a variety of event inputs. Here is how they compare:
| Event Input Action | What It Affects | Event Causes… | Key Difference |
| Normal transfer | Beat | Immediate DMA beat | Event = direct trigger |
| Conditional transfer on strobe | Beat | Transfer only when peripheral also strobes | Requires both event + peripheral |
| Conditional transfer | Beat | Transfer only if condition is met | Event enables but does not force |
| Conditional block transfer | Block | Entire block when condition is met | Block-level gating |
| Channel suspend | Channel | DMA pauses | Flow control |
| Channel resume | Channel | DMA resumes | Restart suspended channel |
| Skip next block suspend | Block suspend logic | Ignore next suspend condition | One-shot override |
| Increase priority | Scheduler | Channel priority boost | Arbitration control |
- Normal Transfer (TRIG) event input is used to trigger a beat or burst transfer to peripherals.
- Conditional Transfer on Strobe (TRIG) event starts or advances a normal DMA transfer. This mechanism is often used when a peripheral, such as a timer or communication module, periodically signals that new data is ready. Periodic triggering allows DMA transfers to align precisely with hardware timing.
- Conditional Transfer Trigger (CTRIG) enables conditional transfers, meaning the DMA channel performs a transfer only when a specific condition associated with the peripheral is met. This is useful when data availability is sporadic or dependent on peripheral state.
- Conditional Block Transfer Trigger (CBLOCK) works at the block level instead of the beat level. Rather than advancing one beat at a time, the DMA channel transfers an entire block when the condition is satisfied. This reduces arbitration overhead and is useful for batch data movement.
- Channel Suspend Operation (SUSPEND) event immediately pauses an active DMA channel. Suspension preserves the channel state and allows transfers to resume later without reinitializing descriptors. This is valuable when higher‑priority operations must temporarily take precedence.
- Channel Resume Operation (RESUME) event restarts a suspended DMA channel. Because state is preserved, the transfer continues exactly where it left off, maintaining data integrity and timing predictability.
- Skip Next Block Suspend Action (SSKIP) event instructs the DMAC to ignore the next suspend condition associated with a block transfer. This provides fine‑grained control over descriptor‑based suspend behavior, particularly in linked descriptor chains.
- Increase Priority (INCPRI) event temporarily raises the priority level of a DMA channel. This allows latency‑sensitive transfers to dynamically preempt lower‑priority traffic in response to real‑time conditions.
DMAC Event Outputs: Signaling System Progress
In addition to consuming events, the DMAC can generate output events that notify other peripherals of transfer progress. Event output generation is enabled using the Channel Event Output Enable bit (CHCTRLB.EVOE), while the specific event condition is selected in the Block Transfer Control register (BTCTRL.EVOSEL).
Here are the output events supported by the DMAC:
- Burst Trigger event is generated when a burst transfer completes. A burst consists of one or more beats transferred contiguously. Burst events are useful when fine‑grained synchronization is required between DMA activity and another peripheral.
- Block Trigger event is generated when an entire block transfer completes. This is the most commonly used output event and is ideal for signaling that a buffer has been filled or emptied.
- Transaction Trigger event is generated when a full DMA transaction completes, including all linked descriptors. This event is particularly useful for multi‑buffer or scatter‑gather transfers, where completion signifies that a complex data movement operation has finished.
How DMAC Events Work in Practice
When an event input occurs, the DMAC evaluates the enabled event actions for the channel. If the action is a trigger, the channel issues a transfer request to the DMAC arbiter. If the action is suspend or resume, the channel state changes immediately. Output events are generated automatically by the DMAC hardware when the configured transfer condition occurs.
Because events are handled entirely in hardware, latency is extremely low and deterministic. This makes DMAC events ideal for real‑time data acquisition, control loops, and communication pipelines.
Benefits of Using DMAC Events
Using DMAC events eliminates unnecessary CPU interrupts, reduces software complexity, and enables true parallelism between computation and data movement. Systems consume less power because the CPU can remain in Sleep modes while DMA transfers are orchestrated by hardware. Event‑driven DMA also improves robustness by reducing timing jitter and software race conditions.
Microchip Technology Solutions and Tools
Microchip Technology provides strong tool support for DMAC events on SAM E51 devices. Atmel® START simplifies configuration of the Event System and DMAC channels through a graphical interface. MPLAB® Harmony v3 includes examples demonstrating event‑driven DMA transfers, including peripheral‑to‑memory and memory‑to‑peripheral use cases. Debugging and event visualization are supported in MPLAB X IDE, with additional insight provided by MPLAB Data Visualizer.
Summary
DMAC events in the SAM E51 microcontroller family enable highly efficient, low‑latency, and low‑power data movement by integrating the Direct Memory Access Controller with the Event System. Event inputs allow hardware to trigger, suspend, resume, or prioritize DMA transfers, while event outputs enable precise synchronization with other peripherals. By leveraging DMAC events, engineers can build responsive, scalable, and power‑efficient embedded systems with minimal CPU involvement.