SAME51 Direct Memory Access Controller (DMAC) Terminology
Last modified by Microchip on 2026/07/10 13:03
| Term | Contextual Explanation |
|---|---|
| Abort transfer | In the SAME51 DMAC, aborting a transfer means gracefully stopping an ongoing or pending DMA operation by disabling a channel or the entire DMAC. The purpose is to prevent data corruption while allowing the current beat to complete and ensuring the write-back descriptor is updated. This is advantageous in embedded systems because it allows safe recovery from changing runtime conditions such as peripheral shutdown or buffer reconfiguration. A common example is stopping a DMA-driven SPI transfer when a chip-select is deasserted early. An abort can be caused by software disabling a channel, disabling the DMAC globally, or entering a low-power mode that requires DMA inactivity. |
| Active channel | The active channel is the single DMA channel currently granted access to the bus by the arbiter. Its purpose is to serialize access to shared system resources such as SRAM and peripherals. This improves system stability and determinism in embedded designs. For example, while multiple channels may be pending, only one active channel performs beat transfers at any moment. A channel becomes active when it wins arbitration due to priority level or round-robin selection. |
| ADDRSTART | ADDRSTART refers conceptually to the initial effective source or destination address used when a DMA block transfer begins. Its purpose is to define where the first beat of data is read or written. This is advantageous because it allows deterministic placement of data streams in memory or peripherals. In practice, ADDRSTART corresponds to the initial programmed SRCADDR or DSTADDR before decrementation and write-back behavior occur, such as starting a UART RX buffer at the end address plus one. |
| Advanced transfer modes | Advanced transfer modes describe DMAC capabilities beyond simple memory copies, such as conditional block transfers, event-triggered transfers, suspend/resume behavior, and linked descriptors. Their purpose is to enable autonomous dataflow without CPU intervention. This greatly reduces power consumption and latency in embedded systems. An example is using an ADC result-ready event to trigger a DMA beat that also emits an event to start the next ADC conversion. |
| AHB (Advanced High-performance Bus) | AHB is the high-speed system bus used by the SAME51 for memory and DMA data transfers. Its purpose is to provide low-latency, high-bandwidth access between masters such as the CPU and DMAC and slaves such as SRAM. This benefits embedded systems by enabling high-throughput DMA transfers without stalling the CPU. For example, the DMAC uses the AHB master interface to move data from SRAM to SERCOM peripherals. |
| AHB/APB Bridge Bus | The AHB/APB bridge connects the high-speed AHB domain to the lower-speed APB peripheral domain. Its purpose is to allow AHB masters like the DMAC to access peripheral registers safely. This separation reduces power and complexity in embedded systems. For example, when the DMAC writes to a SERCOM DATA register, the access passes through the AHB/APB bridge. |
| APB (Advanced Peripheral Bus) | APB is a low-power, low-bandwidth bus used for peripheral register access. Its purpose is to simplify peripheral integration while minimizing power usage. In embedded systems, this allows peripherals like timers or UARTs to be controlled efficiently. An example is the DMAC accessing ADC RESULT or SERCOM DATA registers via APB-mapped addresses. |
| Arbiter | The arbiter is the DMAC logic that decides which DMA channel becomes active when multiple channels request service. Its purpose is to manage contention fairly and deterministically. This improves real-time behavior in embedded systems. For example, a high-priority ADC DMA channel can preempt a lower-priority memory-to-memory transfer after the current beat completes. |
| Arbitration | Arbitration is the process by which the arbiter selects the next active channel based on priority level and scheduling mode. The purpose is to prevent bus conflicts. This is advantageous because it allows predictable latency for critical data streams. Arbitration occurs when multiple channels are pending, after a beat or burst completes, or when a higher-priority request arrives. |
| Asynchronous channel path | An asynchronous channel path refers to DMA transfers that cross different clock domains, such as from a peripheral clock to the system clock. Its purpose is to allow safe data movement despite clock differences. This benefits embedded systems by enabling peripherals like SPI or ADC to operate independently. An example is a SERCOM RX DMA transfer where the peripheral clock is asynchronous to the CPU clock. |
| Atomic | In the DMAC context, atomic refers to operations that cannot be interrupted once started, typically a single beat transfer. The purpose is to ensure data integrity. This is advantageous because arbitration or interrupts cannot corrupt partial data writes. For example, once a DMA beat begins, it completes fully before another channel can preempt it. |
| Background traffic | Background traffic describes DMA transfers that run concurrently with CPU execution without direct CPU involvement. The purpose is to offload repetitive data movement. This improves power efficiency and responsiveness in embedded systems. An example is continuous UART RX into a ring buffer while the CPU sleeps or handles other tasks. |
| Bare metal | Bare metal refers to programming the SAME51 without an operating system, directly controlling hardware registers, including the DMAC. The purpose is maximum control and minimal overhead. This is advantageous in resource-constrained embedded systems. A typical example is configuring DMAC descriptors directly in SRAM for ADC sampling without any RTOS abstraction. |
| BASEADDR | BASEADDR is the DMAC register that points to the base of the descriptor table in SRAM. Its purpose is to tell the DMAC where to fetch the first descriptor for each channel. This enables flexible and fast reconfiguration of DMA behavior. In practice, developers place an array of descriptors aligned in memory and program BASEADDR accordingly. |
| Beat | A beat is the smallest unit of DMA transfer and corresponds to a single bus access. Its purpose is to define granularity. This allows precise control of data width in embedded systems. For example, a beat can be an 8-bit UART byte, a 16-bit ADC sample, or a 32-bit word copy. |
| Beat Count | Beat count is the number of beats in a block transfer, stored in BTCNT. Its purpose is to define how much data is moved in one block. This improves efficiency by reducing interrupt overhead. An example is setting BTCNT to 256 to transfer a full audio buffer from ADC to SRAM. |
| Beat level trigger | A beat level trigger causes a DMA transfer to occur for each trigger event. Its purpose is tight synchronization with peripherals. This is advantageous for streaming data where each peripheral event corresponds to one data unit. For example, each SERCOM RX ready signal triggers exactly one DMA beat. |
| Beat size | Beat size defines the width of each beat, such as 8, 16, or 32 bits. Its purpose is to match the peripheral or memory data width. This avoids alignment issues and improves performance. An example is using 16-bit beats for ADC RESULT registers. |
| Beat transfer | A beat transfer is the execution of a single beat. Its purpose is the atomic movement of one data unit. This benefits embedded systems by ensuring data coherency. For example, transferring one SPI byte from DATA register to SRAM is one-beat transfer. |
| Binary polynomial | A binary polynomial is used by the DMAC CRC engine to compute CRC values. Its purpose is error detection. This is advantageous for validating data integrity without CPU intervention. An example is using the CRC-16 or CRC-32 polynomial to verify a memory block copied by DMA. |
| Block | A block is a group of beats described by one DMA descriptor. Its purpose is to bundle transfers efficiently. This reduces CPU wakeups and interrupts. For example, a block may represent one full UART frame or ADC sample buffer. |
| Block transfer | A block transfer is the execution of all beats in a block. Its purpose is efficient bulk transfer. This is advantageous in embedded systems for moving buffers. An example is copying a 1 kB sensor data block from SRAM to USB endpoint memory. |
| Block Transfer Completion Interrupt | This interrupt is generated when a block transfer finishes. Its purpose is to notify software that data is ready or that resources can be reused. This reduces polling overhead. An example is waking the CPU after a DMA-based ADC buffer fill completes. |
| Block trigger | A block trigger starts or conditions an entire block transfer rather than individual beats. Its purpose is coarse-grained synchronization. This is useful when a single event should initiate a full transfer. An example is starting a memory-to-memory copy when a timer event occurs. |
| BLOCKACT | BLOCKACT is a descriptor field defining what happens when a block completes, such as no action, interrupt, suspend, or both. Its purpose is autonomous flow control. This allows embedded systems to chain operations without CPU involvement. An example is suspending a channel after each block until the software resumes it. |
| BTCNT | BTCNT is the Block Transfer Count register field specifying the number of beats in a block. Its purpose is the precise sizing of transfers. This improves determinism. An example is setting BTCNT to the exact number of bytes expected from a UART transaction. |
| BTCTRL | BTCTRL is the Block Transfer Control field in a descriptor that configures beat size, increment behavior, event output, and validity. Its purpose is to define how the block behaves. This flexibility is advantageous in embedded systems. An example is enabling destination increment while keeping source static for peripheral-to-memory transfers. |
| Burst | A burst is a group of beats treated as one arbitration unit. In SAME51 DMAC, a burst is effectively one beat. Its purpose is arbitration granularity. This ensures fairness and responsiveness. An example is arbitration occurring after each beat transfer. |
| Burst transfer | A burst transfer is the execution of a burst. Its purpose is controlled bus access. This benefits embedded systems by limiting how long a channel can block others. In SAME51, this maps directly to a single beat transfer. |
| Burst trigger | A burst trigger causes a burst to be transferred per trigger. Its purpose is to synchronize DMA with peripheral readiness. This is useful for streaming interfaces. For example, each SPI transmit-ready event triggers one burst, which equals one beat on SAME51. |
| Bus error | In the SAME51 DMAC, a bus error is an error condition that occurs when the DMAC receives an error response from an AHB slave during a data transfer. Its purpose as a detectable condition is to prevent silent data corruption by halting faulty transfers. This is advantageous in embedded systems because it provides a clear fault boundary and allows recovery logic to run. A typical example is attempting to DMA to an unmapped or protected memory region. A bus error represents invalid address access or peripheral unavailability, and it causes the active channel to be disabled with the transfer error flag set. Rectifying the root cause involves validating source and destination addresses, ensuring peripheral clocks are enabled, and confirming correct memory region permissions. |
| Bus master | A bus master is any component capable of initiating transactions on the system bus, and in the SAME51, this includes the CPU and the DMAC. The purpose of having multiple bus masters is to allow parallelism between computation and data movement. This improves throughput and efficiency in embedded systems. For example, while the CPU executes application code, the DMAC acts as a bus master to move ADC samples into SRAM without CPU intervention. |
| Bus matrix | The bus matrix is the interconnect fabric that links bus masters to bus slaves in the SAME51. Its purpose is to manage routing and arbitration between multiple masters and slaves. This architecture is advantageous because it allows concurrent accesses when possible and minimizes bottlenecks. An example is the CPU accessing Flash while the DMAC simultaneously accesses SRAM through different matrix paths. |
| Bus slave | A bus slave is a device that responds to transactions initiated by a bus master. In the SAME51, SRAM, Flash, and peripheral registers act as bus slaves. The purpose of bus slaves is to provide addressable resources. This enables modular embedded designs. For example, the DMAC writes received UART data into SRAM, which acts as an AHB slave. |
| Channel | A DMAC channel is an independent transfer context that defines how data is moved between a source and a destination. Its purpose is to allow multiple concurrent or scheduled DMA operations. This is advantageous in embedded systems because different peripherals can be serviced independently. For example, one channel may handle ADC sampling while another handles SPI transmission. |
| Channel access | Channel access refers to a channel’s opportunity to become active and perform a transfer on the bus. Its purpose is controlled sharing of bus bandwidth. This ensures fairness and predictability in embedded systems. For example, a lower-priority channel may wait until higher-priority channels complete their beats before gaining access. |
| Channel Busy Status Bits | Channel Busy Status Bits indicate whether a DMA channel is currently active or pending. Their purpose is to provide software visibility into DMAC operation. This is advantageous for synchronization and debugging in embedded systems. For example, firmware may poll these bits before reconfiguring a channel to avoid modifying an active transfer. |
| Channel priority type | Channel priority type defines how priority is interpreted during arbitration, typically fixed or round-robin within priority levels. Its purpose is to control latency versus fairness tradeoffs. This is advantageous in real-time embedded systems where critical data streams need guaranteed service. An example is assigning fixed high priority to an ADC channel while using round-robin scheduling for background memory transfers. |
| Channel resume | Channel resume is the action of continuing a previously suspended DMA channel. Its purpose is to allow conditional or staged data transfers. This improves flexibility in embedded systems. For example, a channel suspended after a block transfer can be resumed by software once the buffer is processed. Resumption can also trigger a descriptor fetch, which may cause suspension again if the descriptor is invalid. |
| Channel suspend | Channel suspend is a state where a DMA channel pauses execution without being disabled. Its purpose is controlled flow interruption without losing state. This is advantageous because it avoids full reinitialization. For example, a channel may suspend after completing a block while waiting for software to validate data. |
| Channel Suspend Conditions | Channel suspend conditions are events that cause a channel to enter the suspended state. These include fetching a descriptor with the VALID bit cleared, encountering a null descriptor address, or completing a block with BLOCKACT configured to suspend. Their purpose is safe flow control. This helps embedded systems avoid undefined behavior when descriptor chains are incomplete. |
| CHCTRLB | CHCTRLB is a DMAC channel control register that configures trigger source, trigger action, and priority level. Its purpose is to define how and when a channel operates. This register is advantageous because it centralizes channel behavior configuration. For example, CHCTRLB is used to link a SERCOM RX trigger to a beat-triggered DMA channel. |
| Circular buffer | A circular buffer is a memory structure where the write pointer wraps around to the beginning when the end is reached. Its purpose in DMAC usage is continuous data streaming. This is highly advantageous in embedded systems for uninterrupted data capture. An example is using a circular buffer for UART RX by reloading descriptors that point back to the buffer start. |
| Conditional block transfer | A conditional block transfer is a DMA block transfer that only proceeds when a specified condition is met, such as an event or strobe. Its purpose is synchronized data movement. This reduces CPU intervention in embedded systems. For example, a block transfer may only occur when a timer event signals that a full sensor frame is ready. |
| Conditional transfer | A conditional transfer is any DMA transfer whose execution depends on an external condition rather than occurring immediately. Its purpose is coordination with the system state. This is advantageous for low-power embedded designs. An example is gating a memory copy on an event system signal. |
| Conditional transfer on strobe | This is a specific conditional transfer mode where a strobe signal triggers the transfer. Its purpose is precise synchronization with peripheral timing. This improves determinism in embedded systems. For example, a strobe from a capture timer can trigger DMA movement of timestamp data. |
| Contention | Contention occurs when multiple bus masters or channels request access to the same bus or resource simultaneously. Its purpose as a concept is to describe a normal operating condition that arbitration resolves. Understanding contention is advantageous because it helps designers manage latency. For example, CPU instruction fetch and DMA memory access may contend for SRAM access. |
| CPU | The CPU is the primary processing core that configures and supervises the DMAC but does not perform DMA data movement. Its purpose is control and computation. Offloading transfers to the DMAC allows the CPU to sleep or execute application logic, improving power efficiency. An example is the CPU configuring descriptors and then entering sleep while DMA handles sensor data collection. |
| CRC | CRC, or Cyclic Redundancy Check, is a data integrity mechanism supported by the DMAC. Its purpose is to detect errors in transferred data. This is advantageous in embedded systems that require reliable communication or memory copying. An example is computing a CRC over a firmware image copied by DMA. |
| CRC-32 | CRC-32 is a specific CRC variant using a 32-bit polynomial. Its purpose is stronger error detection compared to smaller CRCs. This is advantageous for larger data blocks. An example is verifying the integrity of data received over a communication interface using DMA-assisted CRC-32 calculation. |
| CRCCHKSUM | CRCCHKSUM is a DMAC register that holds the current or final CRC checksum value. Its purpose is to provide software access to the computed CRC. This avoids CPU-based CRC computation. An example is reading CRCCHKSUM after a DMA block transfer completes to validate data correctness. |
| Data Transfer Bus (AHB) | The Data Transfer Bus is the AHB interface used by the DMAC to move payload data. Its purpose is high-speed data movement. This improves throughput in embedded systems. For example, ADC samples are transferred from peripheral registers to SRAM over this bus. |
| DESCADDR | DESCADDR is the pointer to the next DMA descriptor in a linked list. Its purpose is descriptor chaining. This allows complex transfer sequences without CPU intervention. An example is linking multiple buffer descriptors for continuous audio streaming. A null DESCADDR can cause a channel suspend condition. |
| Descriptor | A descriptor is a data structure in memory that fully defines a DMA block transfer. Its purpose is to abstract the transfer configuration from hardware registers. This improves flexibility and scalability. An example is one descriptor defining a UART RX block and another defining the next buffer. |
| Descriptor execution | Descriptor execution is the process by which the DMAC performs the transfer defined by a descriptor. Its purpose is autonomous operation. This is advantageous because once started, the DMAC can complete complex transfer chains. An example is the sequential execution of multiple memory-to-memory copies defined by linked descriptors. |
| Descriptor fetch | Descriptor fetch is the act of reading a descriptor from memory before execution. Its purpose is to load transfer parameters. This allows dynamic reconfiguration. An invalid fetch can lead to channel suspension. For example, fetching the next descriptor after completing a block. |
| Descriptor Fetch Bus (AHB) | This is the AHB interface used specifically for fetching descriptors from memory. Its purpose is the separation of control and data paths. This improves performance and determinism. For example, while one descriptor is being executed, the next can be fetched efficiently. |
| Descriptor memory | Descriptor memory is the SRAM region reserved for DMA descriptors and write-back descriptors. Its purpose is to store control structures. This is advantageous because descriptors can be modified at runtime. An example is updating a descriptor in memory to change the destination buffer. |
| Descriptor Memory Section Base Address (BASEADDR) | BASEADDR is the DMAC register that defines the base address of the descriptor memory section. Its purpose is to anchor descriptor lookup. This allows flexible memory placement. An example is pointing BASEADDR to an aligned descriptor table in SRAM. |
| Destination address | The destination address is the memory or peripheral address where DMA writes data. Its purpose is to define the target of transfers. This enables autonomous data routing. An example is writing ADC conversion results directly into a memory buffer or transmitting data to a SERCOM DATA register. |
| Deterministic behavior | Deterministic behavior in the SAME51 DMAC refers to the ability to predictably bound the timing and order of DMA operations based on priority, arbitration rules, and trigger sources. Its purpose is to ensure real-time reliability in time-sensitive embedded systems. This is advantageous because designers can guarantee worst-case latency for data transfers, which is essential for control loops or synchronized sampling. An example is configuring a high-priority ADC DMA channel with beat triggers so that each sample is transferred within a known number of cycles regardless of background DMA traffic. |
| Disabled channel | A disabled channel is a DMA channel that is not permitted to perform transfers and does not participate in arbitration. Its purpose is to prevent unintended or unsafe data movement. This is advantageous in embedded systems because channels can be safely reconfigured without risk of partial transfers. For example, firmware typically disables a channel before modifying its descriptor chain. A channel becomes disabled when software clears its enable bit or when a fatal error such as a bus error occurs. |
| DMAC | The DMAC is the Direct Memory Access Controller peripheral in the SAME51 responsible for autonomously transferring data between memory and peripherals or between memory regions. Its purpose is to offload data movement from the CPU. This is highly advantageous in embedded systems because it reduces CPU load, lowers power consumption, and increases throughput. A common example is using the DMAC to continuously move ADC samples into SRAM while the CPU remains in sleep mode. |
| DMAC events | DMAC events are signals generated by the DMAC to the event system, such as block completion or beat completion events. Their purpose is to enable hardware-level synchronization between peripherals without CPU involvement. This improves efficiency and latency in embedded systems. An example is generating an event after a DMA block completes that triggers a timer or another DMA channel. |
| DMAC interrupts | DMAC interrupts are CPU interrupts generated by the DMAC to notify software of conditions such as transfer completion, errors, or event detection. Their purpose is software coordination and error handling. This is advantageous because the CPU only intervenes when necessary. An example is handling a block transfer completion interrupt to process a newly filled buffer. |
| DMAC trigger sources | DMAC trigger sources are hardware signals from peripherals or the event system that initiate DMA transfers. Their purpose is to tightly couple data movement to the peripheral state. This reduces polling and latency. An example is using a SERCOM RX ready signal as a trigger source for a beat-triggered DMA transfer. |
| DSTADDR | DSTADDR is the destination address field in a DMA descriptor that specifies where transferred data is written. Its purpose is to define the sink of a DMA transfer. This allows precise data routing in embedded systems. An example is setting DSTADDR to a SERCOM DATA register for memory-to-peripheral transfers or to a buffer in SRAM for peripheral-to-memory transfers. |
| Dynamic arbitration | Dynamic arbitration refers to arbitration behavior that adapts at runtime based on channel priority and activity, rather than fixed scheduling. Its purpose is to balance responsiveness and fairness. This is advantageous in embedded systems where workloads change over time. An example is allowing a newly activated high-priority channel to preempt lower-priority background transfers after the current beat completes. |
| Edge detect | Edge detect is the mechanism by which a trigger source is recognized on a rising or falling transition rather than a level. Its purpose is to avoid repeated triggering from a sustained signal. This is advantageous for precise synchronization in embedded systems. An example is triggering a DMA transfer only on the rising edge of a timer overflow signal. |
| Endianness | Endianness defines the byte order used when transferring multi-byte data. In the SAME51, the DMAC operates using the system’s endianness and does not perform byte swapping. The purpose of understanding endianness is to ensure data integrity. This is advantageous because software can correctly interpret DMA-transferred data. An example is ensuring that 32-bit samples transferred from memory are interpreted correctly by a peripheral or algorithm. |
| Error detection | Error detection in the DMAC refers to the ability to detect faults such as bus errors or invalid descriptors during transfers. Its purpose is to prevent silent failures. This is advantageous in embedded systems because it enables robust fault handling. An example is detecting an invalid memory access during a DMA transfer and halting the affected channel. |
| Error Detection Interrupt | The Error Detection Interrupt is generated when the DMAC detects a transfer error. Its purpose is to alert software immediately. This improves system reliability by allowing rapid response. An example is invoking an interrupt handler to log a bus error and reset the affected channel. |
| Event | An event is a hardware signal communicated through the SAME51 event system that represents the occurrence of a condition. Its purpose is low-latency, CPU-independent signaling. This is advantageous in embedded systems for power-efficient coordination. An example is a DMA block completion generating an event consumed by a timer or another DMA channel. |
| Event channel | An event channel is a routing path in the event system that connects an event generator to one or more event users. Its purpose is flexible signal distribution. This allows embedded systems to be reconfigured without rewiring hardware. An example is routing a DMAC event to both a timer and another DMA channel. |
| Event Detected Channel Interrupt | This interrupt is generated when a DMA channel detects an incoming event configured as a trigger. Its purpose is optional software notification of event-driven DMA activity. This is advantageous for debugging or mixed hardware-software workflows. An example is logging when an external event caused a DMA transfer to occur. |
| Event generator | An event generator is a peripheral or DMAC function that produces events. Its purpose is to signal state changes or completions. This enables autonomous hardware interactions. An example is the DMAC generating an event when a block transfer completes. |
| Event system | The event system is a hardware interconnect that allows peripherals, including the DMAC, to communicate via events without CPU intervention. Its purpose is to reduce latency and power consumption. This is highly advantageous in embedded systems. An example is chaining ADC conversion, DMA transfer, and timer restart entirely through events. |
| Event trigger | An event trigger is the configuration that causes a DMA transfer in response to an incoming event. Its purpose is hardware-driven control flow. This improves determinism. An example is configuring a DMA channel to start a block transfer when a timer event occurs. |
| Event user | An event user is a peripheral or DMAC channel that consumes an event. Its purpose is to react to system conditions. This allows modular design. An example is a DMA channel acting as an event user to initiate data transfer when an ADC signals completion. |
| Event-driven architecture | Event-driven architecture is a system design approach where actions are triggered by events rather than polling. In the SAME51, the DMAC and event system enable this model in hardware. Its purpose is efficiency and responsiveness. This is advantageous for low-power embedded systems. An example is a sensor sampling pipeline driven entirely by timer and DMA events. |
| Fairness | Fairness refers to the arbitration property that ensures no DMA channel is permanently starved of bus access. Its purpose is balanced resource sharing. This is advantageous in embedded systems with multiple active channels. An example is round-robin arbitration among channels of equal priority. |
| Fetch engine | The fetch engine is the DMAC logic responsible for retrieving descriptors from memory. Its purpose is to load transfer parameters autonomously. This enables descriptor chaining. An example is the fetch engine reading the next descriptor pointed to by DESCADDR after a block completes. |
| FIFO | FIFO, or First-In First-Out, refers to buffering used internally by peripherals or conceptually in DMA-fed data streams. Its purpose is to decouple producer and consumer timing. This is advantageous in embedded systems to smooth data flow. An example is a UART FIFO being serviced by DMA to prevent overflow. |
| GCLK | GCLK, or Generic Clock, provides the clock signal to the DMAC and related peripherals. Its purpose is to control timing and power consumption. This is advantageous because the DMAC can be disabled or slowed by gating its clock. An example is enabling the DMAC clock only when transfers are required. |
| Generator polynomial | The generator polynomial defines the mathematical basis for CRC computation in the DMAC. Its purpose is error detection. This is advantageous because different polynomials provide different detection strengths. An example is selecting a CRC-32 generator polynomial for verifying large data blocks transferred by DMA. |
| Idle channel | An idle channel is a DMA channel that is enabled but not currently transferring data. Its purpose is readiness without activity. This is advantageous because channels can respond immediately to triggers. An example is a channel waiting idle for a peripheral trigger signal. |
| Increase priority | Increase priority refers to configuring a DMA channel with a higher priority level. Its purpose is to reduce latency for critical transfers. This is advantageous in real-time embedded systems. An example is increasing the priority of an emergency sensor DMA channel over background logging transfers. |
| Incremental addressing | Incremental addressing is a mode where the source or destination address is automatically incremented after each beat. Its purpose is sequential memory access. This improves efficiency. An example is incrementing the destination address while writing a buffer of ADC samples to SRAM. |
| Interleaved buffers | Interleaved buffers are multiple buffers used alternately to allow one to be filled while another is processed. Their purpose is continuous data flow. This is advantageous in embedded systems requiring uninterrupted streaming. An example is ping-pong buffering implemented with two DMA descriptors. |
| Invalid descriptor | An invalid descriptor is a descriptor with its VALID bit cleared or with incorrect configuration. This represents a condition where the DMAC must not execute the descriptor. Its purpose is safety and flow control. This is advantageous because it prevents undefined transfers. An invalid descriptor causes the channel to suspend. Rectifying the root cause involves ensuring descriptors are correctly initialized and marked valid before enabling or resuming the channel. |
| Latency | Latency in the SAME51 DMAC context refers to the time between a trigger event and the actual execution of a DMA beat or block transfer. Its purpose as a measurable concept is to characterize responsiveness. Low latency is advantageous in embedded systems because it ensures timely data movement for real-time tasks. For example, minimizing latency is critical when transferring ADC samples triggered by a timer to ensure accurate sampling intervals. Latency is influenced by arbitration, channel priority, and bus contention. |
| Linked descriptors | Linked descriptors are DMA descriptors connected through the DESCADDR field to form a sequence of block transfers. Their purpose is to allow complex transactions consisting of multiple blocks without CPU intervention. This is advantageous in embedded systems because it enables continuous streaming and buffer chaining. An example is implementing a ping-pong buffer for audio capture, where each descriptor points to the next buffer in the sequence. |
| Linked list | A linked list in the DMAC refers to the logical structure formed by chained descriptors in memory. Its purpose is to define the ordered execution of multiple transfers. This structure is advantageous because it supports dynamic and non-uniform transfer patterns. An example is using a linked list of descriptors to transfer scattered sensor data into a contiguous memory region. |
| Non-contiguous memory | Non-contiguous memory refers to memory regions that are not sequentially adjacent in address space. The purpose of supporting such memory through DMA descriptors is flexibility in memory usage. This is advantageous in embedded systems with fragmented SRAM. An example is using multiple linked descriptors to gather data from non-adjacent buffers into a single output stream. |
| Normal transfer | A normal transfer is a standard DMA operation without conditional behavior, suspension, or special triggers beyond the configured trigger source. Its purpose is straightforward data movement. This simplicity is advantageous for predictable and low-overhead transfers. An example is copying a block of memory from one SRAM region to another at system startup. |
| Overrun Channel Interrupt | The Overrun Channel Interrupt is raised when a DMA channel cannot service incoming data fast enough, typically due to sustained trigger events exceeding transfer capability. Its purpose is to signal data loss risk. This is advantageous because software can detect and respond to throughput issues. An example is detecting UART RX overruns when DMA cannot keep pace with incoming data. The root cause can be rectified by increasing channel priority, reducing trigger rate, or enlarging buffers. |
| Pause transfer | Pause transfer refers to temporarily halting an active DMA channel without fully disabling it. Its purpose is controlled flow interruption. This is advantageous in embedded systems where timing or resource constraints require brief suspension. An example is pausing a memory-to-peripheral DMA transfer while reconfiguring the destination peripheral. |
| Pending channel | A pending channel is a DMA channel that has received a trigger but has not yet become active due to arbitration or resource contention. Its purpose is to queue work. This allows multiple channels to request service concurrently. An example is a low-priority logging DMA channel waiting while higher-priority sensor transfers complete. |
| Peripheral trigger | A peripheral trigger is a hardware signal generated by a peripheral to request a DMA transfer. Its purpose is to synchronize data movement with peripheral state. This is advantageous in embedded systems because it eliminates polling. An example is a SERCOM transmit-ready signal triggering a DMA beat. |
| Peripheral-specific memory alignment | Peripheral-specific memory alignment refers to alignment requirements imposed by peripherals for DMA access. Its purpose is to ensure correct and efficient transfers. This is advantageous because misaligned access can cause errors or inefficiencies. An example is aligning 16-bit ADC result buffers on halfword boundaries. Failure to meet alignment requirements can cause bus errors. |
| Preemption | Preemption in the DMAC refers to a higher-priority channel interrupting the scheduling of lower-priority channels after a beat completes. Its purpose is to ensure critical transfers are serviced promptly. This is advantageous in real-time embedded systems. An example is a high-priority emergency sensor DMA channel preempting background memory transfers. |
| Prefetch channel | Prefetch channel refers to the DMAC’s ability to fetch the next descriptor ahead of time while executing the current one. Its purpose is to reduce latency between blocks. This is advantageous in streaming applications. An example is prefetching the next audio buffer descriptor to ensure seamless playback. |
| Quality of Service | Quality of Service in the DMAC context refers to the predictable allocation of bus access and latency based on priority and arbitration configuration. Its purpose is to guarantee performance for critical data flows. This is advantageous in embedded systems with mixed real-time and background traffic. An example is ensuring sensor data DMA maintains guaranteed bandwidth despite other transfers. |
| Real-time embedded system | A real-time embedded system is one where correctness depends on both logical results and timing guarantees. The DMAC supports such systems by providing deterministic data transfers. This is advantageous because it allows the CPU to focus on control logic. An example is a motor control system where DMA ensures timely sampling of current sensors. |
| Real-time traffic | Real-time traffic refers to DMA transfers that have strict timing requirements. Its purpose is to distinguish critical data flows from background transfers. This allows prioritization. An example is ADC or control loop data transfers that must complete within fixed deadlines. |
| Resume transfer | Resume transfer is the action of continuing a paused or suspended DMA channel. Its purpose is to restore operation without reinitialization. This is advantageous because it preserves the transfer state. An example is resuming a DMA channel after software clears a buffer-full condition. |
| Resynchronized channel path | A resynchronized channel path refers to DMA transfers that cross clock domains and are resynchronized internally. Its purpose is safe data movement between asynchronous domains. This is advantageous in embedded systems with multiple clocks. An example is transferring data from a peripheral running on a different clock than the CPU. |
| Round-robin arbitration | Round-robin arbitration is an arbitration scheme where channels of equal priority are serviced in turn. Its purpose is fairness. This is advantageous in embedded systems to prevent starvation. An example is evenly distributing bus access among multiple background DMA channels. |
| Scatter-gather memory | Scatter-gather memory describes the technique of collecting data from scattered memory locations into a contiguous buffer or distributing data from a contiguous buffer into scattered locations. Its purpose is flexible memory management. This is advantageous in embedded systems with fragmented memory. An example is gathering sensor readings stored in different buffers into a single transmission packet using linked descriptors. |
| Seed | The seed is the initial value loaded into the CRC engine before computation. Its purpose is to initialize the CRC calculation. This is advantageous because different seeds support different protocols. An example is setting a protocol-specific seed before calculating a CRC over DMA-transferred data. |
| Skip next block suspend | Skip next block suspend is a configuration that allows a DMA channel to bypass suspension behavior for the next block. Its purpose is fine-grained flow control. This is advantageous in embedded systems with mixed automatic and software-controlled sequencing. An example is skipping suspension to allow continuous execution of a critical transfer sequence. |
| Sleepwalking | Sleepwalking refers to the ability of peripherals and DMAC to operate while the CPU is in sleep mode. Its purpose is ultra-low-power operation. This is highly advantageous in battery-powered embedded systems. An example is the DMAC transferring ADC samples while the CPU remains asleep until a buffer is full. |
| Software intervention | Software intervention refers to CPU involvement in DMA operation, such as configuration, error handling, or buffer processing. Its purpose is system control. Minimizing intervention is advantageous because it reduces power and latency. An example is software handling a DMA completion interrupt to process data. |
| Software shutdown | Software shutdown refers to intentionally stopping DMA operation through firmware. Its purpose is safe system reconfiguration or power-down. This is advantageous because it prevents incomplete transfers. An example is disabling all DMA channels before entering deep sleep. |
| Software trigger | A software trigger is a manually generated trigger that initiates a DMA transfer. Its purpose is controlled activation without hardware events. This is advantageous for testing or one-shot transfers. An example is triggering a memory copy via DMA from firmware. |
| Source address | The source address is the memory or peripheral address from which DMA reads data. Its purpose is to define the origin of transfers. This enables autonomous data movement. An example is reading from an ADC RESULT register or an SRAM buffer. |
| SRAM | SRAM is the primary on-chip memory used for data storage and DMA descriptors. Its purpose is fast, low-latency access. This is advantageous because the DMAC requires descriptors to reside in SRAM. An example is storing DMA descriptor tables and data buffers in SRAM. |
| SRCADDR | SRCADDR is the source address field in a DMA descriptor. Its purpose is to specify where the DMAC reads data from. This allows flexible data routing. An example is setting SRCADDR to a peripheral data register for peripheral-to-memory transfers. |
| Static addressing | Static addressing is a mode where the source or destination address does not change between beats. Its purpose is repeated access to a fixed register. This is advantageous for peripheral access. An example is repeatedly reading from a UART DATA register while writing to incrementing memory addresses. |
| Static arbitration | Static arbitration is an arbitration scheme in which DMA channel priorities are fixed and do not change at runtime. Its purpose in the SAME51 DMAC is to provide predictable channel servicing based solely on configured priority levels. This is advantageous in embedded systems that require deterministic timing, since the order of channel access can be analyzed at design time. An example is assigning a permanently highest priority to a safety-critical sensor DMA channel while all other channels operate at lower priorities. |
| Step size | Step size defines the amount by which the source or destination address is incremented between beats when incremental addressing is enabled. Its purpose is to support strided or structured memory layouts. This is advantageous in embedded systems handling multidimensional data, such as image buffers. An example is stepping the destination address by a fixed stride to store DMA-transferred pixel rows with padding between lines. |
| Strided memory access | Strided memory access refers to DMA transfers where addresses advance by a fixed stride rather than contiguously. Its purpose is efficient handling of structured data layouts. This is advantageous because it avoids CPU-based reformatting. An example is transferring every Nth sample from a sensor buffer into another memory region for downsampling. |
| Suspend-and-resume | Suspend-and-resume is a DMAC operational pattern where a channel intentionally suspends execution and later continues from the same state. Its purpose is controlled, staged data movement. This is advantageous in embedded systems that must synchronize DMA activity with software processing. An example is suspending a channel after filling a buffer and resuming it once the CPU has processed the data. |
| Suspended channel | A suspended channel is a DMA channel that has halted execution but retains its internal state. Its purpose is to allow safe pausing without full teardown. This is advantageous because reconfiguration or synchronization can occur without restarting transfers. A channel can become suspended due to BLOCKACT configuration, encountering an invalid descriptor, or explicit software action. |
| Synchronized channel path | A synchronized channel path refers to DMA transfers that operate within a single clock domain or are explicitly synchronized to a common clock. Its purpose is simplified timing analysis and reduced latency. This is advantageous in embedded systems where peripherals and memory share the same clock. An example is a memory-to-memory DMA transfer fully synchronized to the system clock. |
| Termination | Termination in the DMAC context refers to the final stopping of a DMA channel after completing its current transfer or due to an error. Its purpose is to safely end DMA activity. This is advantageous because it prevents partial or corrupted transfers. Termination can occur after a normal transfer completes, after an abort, or due to an unrecoverable error such as a bus error. |
| Transaction | A transaction is a logical DMA operation consisting of one or more transfers defined by descriptors. Its purpose is to group related data movements. This abstraction is advantageous because it allows complex operations to be treated as a single unit. An example is treating the capture of one full sensor frame as a single DMA transaction composed of multiple blocks. |
| Transaction complete | Transaction complete is the condition where all transfers associated with a DMA transaction have finished. Its purpose is to signal readiness for post-processing or reconfiguration. This is advantageous in embedded systems because software or events can be triggered only when the entire operation is done. An example is generating an interrupt after all linked descriptors in a chain have executed. |
| Transaction-level trigger | A transaction-level trigger initiates or controls DMA behavior at the transaction granularity rather than per beat or block. Its purpose is coarse-grained synchronization. This is advantageous when a single trigger should cause a full multi-block operation. An example is starting a complete buffer transfer in response to a timer event. |
| Transaction trigger | A transaction trigger is the event or signal that causes a DMA transaction to begin. Its purpose is to align data movement with system events. This is advantageous because it enables event-driven data pipelines. An example is using an external interrupt event to trigger a full DMA transaction that captures sensor data. |
| Transfer | A transfer is the fundamental DMA operation that moves data from a source address to a destination address. Its purpose is to offload data movement from the CPU. This is advantageous in embedded systems because it reduces CPU load and power consumption. An example is transferring a block of UART-received bytes into an SRAM buffer. |
| Transfer count | Transfer count is the total number of beats or data units to be transferred. Its purpose is to define transfer length. This is advantageous because it allows precise sizing of operations. An example is setting the transfer count to match the exact number of samples expected from an ADC conversion sequence. |
| Transfer definitions | Transfer definitions describe how transfers are categorized and structured, including beats, blocks, bursts, and transactions. Their purpose is to provide a consistent conceptual model. This is advantageous for designing and debugging DMA behavior. An example is understanding that a block consists of multiple beats and a transaction may consist of multiple blocks. |
| Transfer descriptor | A transfer descriptor is a memory-resident structure that defines a DMA block transfer, including addresses, counts, and control fields. Its purpose is to describe transfers independently of hardware registers. This is advantageous because it enables descriptor chaining and dynamic reconfiguration. An example is a descriptor defining a peripheral-to-memory ADC data block transfer. |
| Transfer trigger | A transfer trigger is the mechanism that causes a DMA transfer to occur, such as a peripheral signal, event, or software trigger. Its purpose is to synchronize data movement with system activity. This is advantageous in embedded systems for real-time responsiveness. An example is triggering a DMA beat when a SERCOM transmit buffer becomes empty. |
| Trigger | A trigger is any signal that initiates DMA activity. Its purpose is to decouple data movement from CPU control flow. This is advantageous because it enables autonomous operation. Triggers can be generated by peripherals, software, or the event system. |
| WRBADDR | WRBADDR is the DMAC register that specifies the base address of the write-back descriptor memory section. Its purpose is to define where the DMAC stores updated descriptor state. This is advantageous because software can inspect the completed transfer state. An example is reading back the final SRCADDR and DSTADDR after a block completes. |
| Write-back Bus (AHB) | The write-back bus is the AHB interface used by the DMAC to write descriptor state back to memory. Its purpose is to update descriptor fields such as remaining transfer count. This is advantageous because it allows software to observe progress and results. An example is the DMAC writing updated BTCNT values to write-back memory. |
| Write-back descriptor | A write-back descriptor is a copy of the active descriptor that the DMAC updates as transfers progress or complete. Its purpose is to preserve original descriptors while reporting status. This is advantageous for debugging and buffer management. An example is using write-back descriptors to determine how many beats were transferred before suspension or error. |
| Write-back logic | Write-back logic is the internal DMAC mechanism that updates write-back descriptors during and after transfer execution. Its purpose is state tracking. This is advantageous because it enables safe descriptor reuse. An example is automatically updating destination addresses in the write-back descriptor after each block. |
| Write-back memory | Write-back memory is the SRAM region allocated for write-back descriptors. Its purpose is to store transfer results and state. This is advantageous because it allows the CPU to inspect DMA outcomes without interfering with active descriptors. An example is dedicating a section of SRAM for write-back descriptor storage. |
| Write-back memory Section Base Address (WRBADDR) | This refers conceptually to the base address of the write-back memory section defined by the WRBADDR register. Its purpose is to anchor write-back descriptor storage. This is advantageous because it separates control metadata from active descriptor definitions. An example is configuring WRBADDR to point to a dedicated write-back descriptor table aligned in SRAM. |
Learn More
- 32-bit Arm® Cortex®-M4F MCUs with 1 Msps 12-bit ADC, QSPI, USB, Ethernet, and PTC: SAM D5x/E5x Family Data Sheet
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