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dsPIC33A 12-bit 40MSPS Analog-to-Digital Converter (ADC) Deep Dive

ADC Latency

Last modified by Microchip on 2026/03/31 11:41
   Pipelined Architecture  Latency Considerations   

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What is Latency?

For an Analog-to-Digital Converter (ADC), latency is the time interval between when a peripheral or software initiates an ADC conversion request via trigger and when the resulting digital data becomes available in the data register. This metric is critical for real-time and high-speed applications, as it determines how quickly the system can respond to new input signals.

Low ADC latency ensures fast data availability, which is essential for applications requiring rapid signal processing and real-time control.

  • ADC pipeline latency
    • Minimum sampling time (@ 80 MHz CLK): The shortest possible sampling period is 6.25 ns or (0.5 x 12.5 ns).
    • Best case scenario: If the ADC is ready and not processing other conversions, the total latency is about five clock cycles, or 65 ns.
    • Worst case scenario: If the ADC is busy with other conversions, the latency can extend to about seven clock cycles, or 90 ns.
  • Core latency
    • After the sampling period ends, the digital conversion result is available in 2.5 clock cycles.