Configuring the dsPIC33CH Main Project in MPLAB® Code Configurator (MCC) Melody

Last modified by Microchip on 2024/04/10 14:20

Contents

Secondary Core Selection and Configurations
Configuring the Secondary Core Settings
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Setting up the main project involves selecting the Secondary Core and configuring it. The following sections explain the steps involved in setting up the Secondary Core within the main project.

This article details the steps for setting up the main project using the Melody version of MPLAB^® Code Configurator (MCC). If you are using the MCC Classic version, please refer to "Configuring the dsPIC33CH Master Project in MPLAB® Code Configurator (MCC) Classic".

Note: The Secondary Core's oscillator, ICD, WDT, and DMT configurations are not applicable for dual-core devices that have a Secondary Core with its own Flash since all these config-bits reside in the Secondary Core itself.

Flow diagram of steps involved in setting up the Main core

Secondary Core Selection and Configurations

To select the Secondary core for configuration:

Create an MPLAB^® X IDE project for the Main device selected from the dsPIC33CH family.

Launch MCC by:

Clicking on the MCC icon in MPLAB X IDE, or
Navigating to Tools > Embedded > MPLAB Code Configurator v5: Open/Close.

Secondary Core appears in the Project Resource area of MCC in a main project.

Secondary core automatically shows as a project resource in MCC

In the Secondary Core1 module UI, enable Configure Secondary Core.

Enable Configure Secondary Core

Configuring the Secondary Core Settings

Config bits settings are available for the secondary peripherals listed.

Secondary's Clock
MSI
Secondary's ICD
Secondary's Watchdog Timer
Secondary's Deadman Timer
Secondary's Alternate I2C1 Pin Mapping
Secondary's SPI1 Pin Mapping
Secondary's Context Interrupts
Assigning Output Pin Ownership to Secondary Core

Note: Only MSI Configurations and Output Pin Ownership are configurable as part of Secondary Core UI for dual-core devices which has Secondary core with its own Flash. Refer to the device datasheet for more details.

The Secondary Core Settings List

Naming the Secondary Project

The Secondary core's MPLAB X IDE project name is used to include a secondary project image header in the main project-generated code.

Entering the Secondary core's project name

Configuring the Secondary Oscillator

These settings in MCC allow you to configure the required Clock Source, Clock Switching, and Fail-Safe Monitor for the Secondary core.

Clock Source	This allows you to select the required clock source such as Primary Oscillator, FRC Oscillator, FRC Oscillator with PLL, External Clock, Primary Oscillator with PLL, LPRC Oscillator, BFRC Oscillator, and FRC Oscillator with Postscaler depending on the application. The clock source options may vary with the device used.
Enable Clock Switching	This allows you to enable the clock-switching feature.
Enable Fail-Safe Monitor	This allows you to enable or disable the fail-safe monitor feature. When enabled, the fail-safe monitor allows the device to continue to operate even in the event of an oscillator failure.

Secondary Core clock source settings

Note: The Enable Fail-Safe Monitor option only becomes available if Clock Switching is enabled.

Configuring MSI

The MSI is the data gateway between the Main core and the Secondary core, each of which operates within independent clock domains. The MSI module is primarily intended to move data between the cores.

The Mailbox Configuration table provided in MCC allows you to:

Configure handshake protocols by selecting the buffer size. Based on the selected buffer size, MCC allocates a set of mailbox registers to the specific protocol.
Define the direction of data flow, whether from M → S (Main to Secondary) or S → M (Secondary to Main).
Optionally, assign a custom name to each protocol. This custom name is used as part of Application Programming Interface (API) signatures for the protocol in the generated MCC code.

The MSI mailbox configuration table

Configuring Secondary In-Circuit Debugging (ICD)

These settings in MCC allow you to select pins used for in-circuit debugging of the Secondary core. You must select Programming Clock (PGC) and Programming Data (PGD) pins based on the hardware used.

ICD pin selection

Configuring Secondary Watchdog

These settings allow you to configure the Secondary core's watchdog timer:

Watchdog Timer settings

Configuring Secondary's Deadman Timer

These settings allow you to configure the Secondary core's Deadman Timer:

Secondary Deadman Timer settings

Configuring Secondary's Alternate I2C Pins

These settings allow you to configure the Alternate I2C Pins for Secondary's I2C:

Secondary Alternate I2C pin settings

Configuring Secondary SPI Pin Mapping

These settings allow you to configure the Secondary SPI Pin mapping:

Secondary SPI pin settings

Configuring Secondary Context Interrupts

These settings allow you to configure the Secondary Alternate Working registers to a specific Interrupt Priority Level (IPL1 through IPL6) by configuring the CTXTx[2:0] bits:

Secondary Context Interrupts settings

Assigning Pin Ownership to the Secondary Core

Main and Secondary cores share the input/output (I/O) ports on the device. The input feature is available to both the cores, whereas the output feature is decided as per the ownership fuses. By default, the output ownership of a pin resides with the Main core. If the Secondary core needs the output ownership of a particular pin, the ownership configurations have to be changed. Both the Main and the Secondary core(s) can monitor a pin as an input as long as the monitoring is of the same type—digital or analog.

The ownership of output port pins can be modified in the Secondary Core1 settings pane by opening a port dialog box and then selecting the desired pin(s) of that port.

Setting pin ownership for Port A