Hello FPGA
3rd Generation Architectural Blocks
Overview of Microchip FPGA Product Families | 4th Generation Architecture |
3rd Generation Flash FPGA Portfolio
As you explore the third-generation flash-based FPGAs shown in Figure 1, you'll find multiple families to choose from, each tailored to your specific performance and power requirements.
Highest Performance
Your highest performance option is the ProASIC® 3 family, with logic densities ranging from 330 to 35,000 logic elements, suitable for applications that demand low power and high performance. These devices are also available for robust applications in automotive and military temperature grades.
Lowest Power Requirements
For the lowest power requirements, the IGLOO® family is your go-to choice. Built on the ProASIC 3 architecture but with modifications to minimize static and dynamic power, IGLOO devices match the logic densities of the ProASIC 3 family and feature the Flash*Freeze mode, allowing you to enter and exit an ultra-low power state while preserving Static Random Access Memory (SRAM) and registered data.
I/O Intensive and Power Conscious
If your applications are input/output (I/O) intensive and power-conscious, consider the IGLOO PLUS devices. They provide more I/Os per logic element than the standard IGLOO family and come in logic densities from 330 to 1,500 logic elements, all with the Flash*Freeze low power mode.

Figure 1: 3rd Generation FPGA Porfolio
Higher Performance with Reduced Power Consumption
When you need higher performance with reduced power consumption, the ProASIC 3L family provides an effective solution. These devices deliver 40 percent lower dynamic and 50 percent lower static power when compared to ProASIC 3 devices of equivalent size. They are available in various sizes, with logic densities ranging from 7,000 to 35,000 logic elements. Additionally, they include the Flash*Freeze mode feature for power savings.
High Volume Low Power and Small Packaging
For high-volume applications where low power and small packaging are critical, your options include ProASIC 3 and IGLOO nano devices. These are available in logic densities from 100 to 3,000 logic elements and come in compact packages as small as 3 by 3 mm, with IGLOO nano featuring Flash*Freeze mode.
ProASIC 3 and IGLOO Architecture
The block diagram of the ProASIC 3 and IGLOO architecture, shown in Figure 2, will show you the In-System Programming (ISP) Advanced Encryption Standard (AES) decryption block that secures programming by decrypting the bitstream. Each ProASIC 3, IGLOO, and SmartFusion® device includes a 1K-bit block of non-volatile flash read-only memory, which you can reprogram using a programmer or an external microprocessor. This memory is read-only from the FPGA fabric and can store critical data such as IP addresses, calibration settings, serialization information, and versioning, with encryption available for added security.
The Flash*Freeze block, available on all IGLOO and ProASIC 3L devices, allows you to manage the Flash*Freeze low power mode, while the charge pumps generate the necessary internal voltages for programming and erasing the flash interconnect.
At the heart of the architecture are the logic elements, which you can use to implement a 3-input lookup table or a D flip-flop. The I/Os, organized in banks around the die's periphery, support multiple standards from 1.2 volts to 3.3 volts. The red boxes indicate the Phase Locked Loop (PLL) locations and the blue rectangles represent the SRAM blocks, which can be configured as 2-port memory, dual-port memory, or First In, First Out (FIFO). Note that the smallest ProASIC 3 and IGLOO devices do not include SRAM blocks or PLLs.

Figure 2: ProASIC 3 and IGLOO Architecture
Power Comparison
When comparing the IGLOO and ProASIC 3 families for your design requirements, consider the following:
- If the lowest power is paramount, IGLOO, IGLOO nano, or IGLOO PLUS devices are your best choices.
- For a balance of performance and low power, ProASIC 3L devices stand out.
- If your design constraints include small packaging, IGLOO nano devices are ideal.
- For designs needing more than 71 I/Os, IGLOO PLUS devices offer an optimal configuration.
- For high performance in a small package, ProASIC 3 nano devices are worth considering.
For designs that require both low power and high I/O counts, IGLOO PLUS devices offer the highest ratio of I/O to logic elements. If your project demands low power coupled with high performance, ProASIC 3, ProASIC 3 nano, or ProASIC 3L devices should be at the top of your list. Your final selection can be refined based on the number of logic elements, I/Os, and packaging preferences.

Figure 3: Power Comparison
SmartFusion® FPGA
SmartFusion® System on Chip (SoC) FPGAs are based on the 3rd generation flash architecture. They have the same FPGA logic and SRAM blocks as ProASIC 3 and IGLOO devices and add a hard microcontroller subsystem and analog blocks.
The microcontroller subsystem includes:
- 100 megahertz Arm® Cortex®-M3 microcontroller
- 64K bytes of embedded SRAM
- 28k, 256k, or 512K bytes of embedded flash memory
Peripherals include:
- 10/100 Ethernet Media Access Control (MAC)
- Two timers
- Two Serial Peripheral Interface (SPI)
- Two Universal Asynchronous Receiver/Transmitters (UARTs)
- Two I2C blocks
SmartFusion SoC FPGAs have a peripheral Direct Memory Access (DMA) controller for moving data and the 1K bit block of flash ROM that's available in ProASIC 3 and IGLOO devices.
The SmartFusion SoC FPGA analog subsystem includes up to three analog-to-digital converters with 1 percent accuracy and up to three digital-to-analog converters and signal conditioning blocks containing a voltage monitor, a current monitor, and a temperature monitor.
The analog compute engine offloads the CPU from initializing the analog-to-digital converters and processing the analog-to-digital conversion and digital-to-analog conversion results.

Figure 4: SmartFusion Architecture
You can also find this training in video format from Microchip University as "Hello FPGA".