Hello FPGA

Overview of Microchip FPGA Product Families

Last modified by Microchip on 2025/01/31 12:22

   Advantages of Microchip FPGAs  3rd Generation Architectural Blocks   

Introduction

In this training, you'll get an overview of three generations of Microchip's flash Field Programmable Gate Arrays (FPGAs) shown in Figure 1. You'll start with the third-generation ProASIC® 3, IGLOO®, and SmartFusion® families. These are very low-density devices that you can use in place of Complex Programmable Logic Devices (CPLDs). After that, you'll explore the 4th generation low-density IGLOO 2 and SmartFusion 2 families. Then you'll learn about the 5th generation mid-range PolarFire® FPGA and PolarFire System-on-Chip (SoC) families.

All of these families are very low power, have a programming element that is immune to Single Event Upsets (SEUs), and are live at power-up.

Logic Density Graph

Figure 1: FPGA Generations

Summary

Figure 2, shows a summary of the features of the 3rd, 4th, and 5th generation flash FPGA families:

Generation Table

Figure 2: Features by Generation

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3rd Generation

ProASIC 3 and IGLOO FPGAs are CPLD replacements fabricated at 130 nanometers. These families offer between 100 logic elements and 35,000 logic elements and up to 620 I/Os capable of 400 megabits per second for Low-voltage Differential Signaling (LVDS). They have a maximum of 504 Kbits of embedded Static Random-Access Memory (SRAM) in the FPGA fabric, and one or six Phase-Lock Loops (PLLs).

SmartFusion SoC FPGA is based on the 3rd generation architecture. It uses the same FPGA fabric as ProASIC 3 and adds a hard 100 megahertz Arm® Cortex®-M3 processor subsystem with peripherals and embedded flash memory.

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4th Generation

The SmartFusion 2 and IGLOO 2 families are low-density FPGAs, fabricated at 65 nanometers. SmartFusion 2 and IGLOO 2 devices offer up to 150,000 logic elements, up to 240 math blocks for Digital Signal Processing (DSP) operations, and five megabits of embedded SRAM. There's a maximum of 574 I/Os that operate at up to 667 megabits per second for Double Data Rate (DDR), and 750 megabits per second for LVDS. SmartFusion 2 and IGLOO 2 devices have two, six, or eight PLLs and transceivers that operate between one gigabit per second and five gigabits per second. SmartFusion 2 SoC FPGA features a hard 166 megahertz Arm Cortex-M3 subsystem with peripherals and embedded flash memory. Soft processor cores based on the RISC-V instruction set architecture are available for use in these devices.

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5th Generation

PolarFire mid-range FPGAs are fabricated at 28 nanometers. PolarFire FPGAs offer up to 480,000 logic elements, 1,480 math blocks, and 33 megabits of embedded SRAM. Each PolarFire device has eight PLLs, eight Delay Lock Loops (DLLs), and 56 Kbytes of embedded flash memory. They have up to 584 I/Os that can operate at 1,600 megabits per second for DDR4 and LVDS. PolarFire family transceivers operate between 250 megabits per second and 12.7 gigabits per second. Soft RISC-V processor cores and a soft Arm Cortex-M1 processor core are available for PolarFire devices. Devices are available with a hard Athena TeraFire® Crypto Co-processor for data security applications.

PolarFire SoC is based on the PolarFire FPGA architecture and it adds a hard 5-core 64-bit RISC-V CPU cluster with peripherals and two megabits of L2 cache, allowing it to support Linux® and real-time applications. PolarFire SoCs offer up to 460,000 logic elements and up to 636 I/Os.

Video Course

​This course is also available in video format at Microchip University as Hello FPGA.

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