Review SAM E51 DMAC Arbitration
Introduction
The Direct Memory Access Controller (DMAC) in the SAM E51 family of microcontrollers from Microchip Technology allows multiple data transfers to occur independently of the Central Processing Unit (CPU). When more than one Direct Memory Access (DMA) channel wants access to memory or a peripheral at the same time, a decision must be made about who goes next. That decision-making process is called arbitration.
This lesson explains why arbitration exists, how it operates inside the SAM E51 DMAC, how priority and fairness are enforced, and how Quality of Service (QoS) settings influence system behavior.
Purpose and Advantages of Arbitration
Arbitration exists to safely and predictably share limited system resources. In the SAM E51, DMA channels compete for access to buses that connect Static Random-Access Memory (SRAM), peripherals and the system interconnect. Without arbitration, simultaneous access attempts would lead to conflicts and undefined behavior.
The advantages of the DMAC arbitration system are determinism, scalability and flexibility. Arbitration ensures that time‑critical transfers can be prioritized, background transfers can coexist without starving important ones, and multiple peripherals can stream data concurrently with minimal CPU intervention. Proper use of arbitration directly improves real‑time responsiveness and overall system throughput.
How DMAC Arbitration Works
When a DMA channel is enabled and not suspended, and it receives a transfer trigger from a peripheral or software, it issues a transfer request to the DMAC arbiter. The arbiter is the hardware logic that decides which channel is allowed to perform the next data movement.
Once the arbiter receives a transfer request, the channel is added to an internal queue of channels with pending transfers. At the same time, the corresponding Pending Channel x bit in the Pending Channels register (PENDCH.PENDCHx) is set, indicating that channel x is waiting for service.
Based on the configured arbitration rules, the arbiter selects one channel as the active channel. The next transfer descriptor for that channel is fetched from SRAM and loaded into an internal structure called the prefetch channel. The active channel is the one currently granted access to perform its next burst transfer, where a burst is one or more data beats transferred back‑to‑back.
After the active channel completes a burst transfer, the descriptor held in the prefetch channel is promoted into the active channel, and the next burst begins. When this promotion occurs, the corresponding PENDCH.PENDCHx bit is cleared. Depending on the channel’s trigger action configuration and whether additional bursts are required, the Busy Channel x bit in the Busy Channels register (BUSYCH.BUSYCHx) will either be set or remain set to indicate that the channel is still active.
When a channel finishes its granted burst transfers, several outcomes are possible. The channel may be returned to the pending queue if more transfers remain, it may wait for a new trigger, it may be suspended or it may be disabled. If the channel enters a waiting, suspended, or disabled state, the BUSYCH.BUSYCHx bit is cleared.
If a channel is suspended while it still has a pending transfer, it is removed from the pending queue, but its PENDCH.PENDCHx bit remains set. This suspended condition is also reported in the Channel Interrupt Flag register (CHINTFLAGn.SUSP). When the channel is resumed, it is automatically reinserted into the pending queue. If a channel is disabled by clearing CHCTRLA.ENABLE while it has a pending transfer, it is removed from the queue and its PENDCH.PENDCHx bit is cleared entirely.
Channel Priority and Arbitration Levels
The SAM E51 DMAC supports a multi‑level priority scheme to control arbitration decisions. Each DMA channel is assigned a priority level, configured using the Channel Priority Level register (CHPRILVL.PRILVL). When a channel is pending or actively transferring data, the corresponding Level Executing bit in the Active Channel and Levels register (ACTIVE.LVLEXx) is set.
Up to four priority levels are supported, although the exact number may vary by device family. A higher numerical priority level always wins over a lower one, as long as that level is enabled. Priority levels are enabled individually using the Priority Level Enable bits (CTRL.LVLENx) in the DMAC Control register.
Arbitration is performed after every burst transfer. This design allows the DMAC to rapidly respond to changing system demands and ensures that high‑priority channels can preempt lower‑priority ones between bursts.
Within each priority level, the arbiter can operate in either static or dynamic (round robin) mode.
Static Versus Dynamic Arbitration
In static arbitration, lower channel numbers are given preference within the same priority level. While simple and predictable, this approach carries the risk that higher‑numbered channels may rarely, or never, be granted access if lower‑numbered channels continuously request transfers.
In dynamic arbitration, also known as round robin arbitration, the last channel granted access is given the lowest priority for the next decision. This ensures fairness by rotating access among channels at the same priority level. Dynamic arbitration prevents starvation and is generally preferred when multiple channels perform similar workloads.
What Happens When Access Is Granted
If the same channel continues to be granted access, its Block Transfer Count (BTCNT) is decremented, an optional output beat event may be generated and a new burst transfer begins immediately.
If a different channel is granted access, the current channel’s status is written back to its write‑back descriptor in SRAM. The first transfer descriptor of the newly selected channel is fetched into internal memory, and a new burst transfer begins under the control of that channel.
Transfer QoS
Beyond channel priority, the SAM E51 DMAC supports transfer QoS to influence how aggressively transfers are handled on the system buses. Each priority level group has dedicated QoS settings, configured in the Priority Control registers (PRICTRLx.QOSn).
When a channel is stored in the prefetch channel or active channel, its QoS value is latched internally. The DMAC then selects the highest QoS value between the active and prefetch channels, and this value is applied to all DMAC bus accesses. Higher QoS values reduce latency and improve responsiveness when competing with other bus masters such as the CPU or USB controller.
QoS is particularly valuable in systems with mixed real‑time and background traffic, ensuring that latency‑sensitive DMA transfers meet timing requirements even under heavy system load.
Benefits of DMAC Arbitration and QoS
The arbitration system in the SAM E51 DMAC delivers predictable real‑time behavior, efficient bus utilization and strong isolation between critical and non‑critical transfers. Priority levels allow urgent data streams to meet deadlines, while dynamic arbitration ensures fairness. QoS adds another dimension of control, enabling designers to tune memory and peripheral access latency with precision. Together, these features enable high‑performance, low‑power embedded designs.
Microchip Technology Solutions
Microchip Technology supports SAM E51 DMAC development through Atmel START, which can automatically configure DMA channels, priorities and arbitration modes. MPLAB® Harmony v3 provides reusable drivers and examples that demonstrate multi‑channel DMA usage with priority and QoS considerations. Comprehensive SAM D5x/E5x Family Data Sheet and online documentation further detail arbitration behavior and recommended design practices.
Summary
Arbitration in the SAM E51 DMAC ensures that multiple DMA channels can safely and efficiently share system resources. By combining priority levels, static or dynamic arbitration and QoS controls, the DMAC provides fine‑grained control over how and when data moves through the system. Understanding and correctly configuring these mechanisms is essential for building responsive, scalable and power‑efficient embedded applications on the SAM E51 platform.