Learn How SAM E51 DMAC Transfer Controls Work
Introduction
Moving data efficiently is as important as processing it. In embedded systems, poorly managed data movement wastes Central Processing Unit (CPU) cycles, increases power consumption and complicates real‑time behavior. The Direct Memory Access Controller (DMAC) in the SAM E51 microcontroller from Microchip Technology addresses this problem by autonomously moving data between memory and peripherals.
This chapter explains transfer control in the SAM E51 DMAC: how transfers start, how addresses are managed, how performance is optimized with internal buffering, how errors are detected and how completion is signaled. By the end, you will learn about the life cycle of a Direct Memory Access (DMA) transfer from trigger to completion and how the DMAC maintains correctness even when transfers are interrupted.
Overview of Transfer Control
A DMA transfer is not a single action but a controlled sequence managed by hardware. The SAM E51 DMAC contains an arbiter, fetch engine, internal First‑In, First‑Out (FIFO) and write‑back logic, all coordinated to ensure reliable and high‑performance data movement.
A transfer always begins with a trigger, proceeds through descriptor execution and ends with optional interrupts or events. Throughout this process, the DMAC maintains internal state so that transfers can be paused, resumed, or safely aborted when necessary.
Transfer Sequence
A DMA transfer sequence begins when a transfer trigger is detected. A trigger is a request for data movement generated by software, a peripheral, or the Event System (EVSYS), which is a hardware routing network for signals between peripherals.
Once a trigger occurs, the DMAC arbiter evaluates all active DMA channels and selects one based on priority. Only one channel may access the bus at a time.
After a channel is granted access, the DMAC fetch engine retrieves a descriptor from Static Random‑Access Memory (SRAM). A descriptor is a data structure that defines source address, destination address, transfer size, addressing mode and control options.
For a new block transfer, the descriptor address is taken from BASEADDR, which points to the first descriptor in the channel’s list. If a transfer is interrupted by a higher‑priority channel, the DMAC saves the current state into a write‑back descriptor located at WRBADDR. This allows the interrupted transfer to resume exactly where it left off.
During execution, the transfer may generate output events, interrupts, or both. The SAM E51 DMAC also includes a Cyclic Redundancy Check (CRC) engine, which can be enabled to detect data corruption during transfers.
Descriptor Fetch and Write‑Back Mechanism
Descriptors reside in SRAM and are fetched into the DMAC’s internal memory before execution. When a transfer is preempted, the DMAC automatically writes the updated descriptor state back to the location pointed to by WRBADDR.
This mechanism is essential for reliable preemption. Without write‑back descriptors, partially completed transfers would lose their progress. Instead, the SAM E51 DMAC guarantees that even interrupted block transfers can resume without software intervention.
Addressing Modes
Every block transfer requires both a source address and a destination address. These addresses may be fixed or incremented depending on the application.
Static addressing is used when accessing peripheral registers, such as a Universal Synchronous/Asynchronous Receiver/Transmitter (USART) data register. Incremental addressing is used when transferring arrays or buffers in memory.
The SAME51 DMAC supports independent increment control for source and destination. Address incrementation follows this formula:
Here, ADDRSTART is the source or destination address of the first beat in the block transfer. BTCNT is the initial number of beats in the block. BEATSIZE is the number of bytes per beat (1, 2, or 4B). STEPSIZE is a register value from 0 to 7 that determines how many beats occur between address increments, where a value of 0 corresponds to one beat.
This flexible addressing scheme enables advanced patterns such as strided memory access, interleaved buffers and peripheral‑specific alignment requirements.
Internal FIFO Operation
To improve bandwidth and reduce bus contention, the SAM E51 DMAC includes an internal FIFO buffer. The FIFO decouples read and write operations, allowing the DMAC to batch transfers efficiently.
When the channel is configured for single‑beat bursts (BURSTLEN = SINGLE), the DMAC waits until the FIFO can transmit or accept one beat before requesting bus access. In all other burst configurations, the DMAC waits until the FIFO reaches a configurable threshold before requesting access to write data to the destination.
If the DMAC completes all read operations before the FIFO reaches the threshold, writes are automatically enabled to drain the FIFO. If the FIFO becomes empty while reads are still ongoing, the DMAC waits again until the threshold is reached.
This behavior maximizes throughput while minimizing unnecessary bus arbitration, especially during large memory transfers.
Error Handling
The SAM E51 DMAC includes robust error detection mechanisms to ensure system reliability.
A bus error occurs when an invalid or inaccessible address is accessed. This condition can optionally generate a transfer error interrupt, allowing software to respond immediately.
An invalid descriptor error occurs if the descriptor format or address is incorrect. In this case, the DMAC sets the Channel Fetch Error status bit and may optionally generate a channel suspend interrupt. Suspending the channel prevents further damage while preserving system stability.
Transfer Triggers
Transfers can be initiated in several ways. Software triggers allow explicit control from firmware. Peripheral triggers automatically start transfers when hardware conditions occur, such as an ADC result becoming ready. Event triggers allow transfers to be chained through the Event System without CPU involvement.
By default, triggers initiate block transfers, but the SAM E51 DMAC also supports beat‑level and transaction‑level triggering when configured.
To monitor activity, the DMAC provides Channel Busy Status Bits, which allow software to determine whether a channel is active, pending, or idle.
Linked List Completion
When linked descriptors are used, the channel automatically fetches and executes each descriptor in sequence. If the linked list is not empty, the channel waits for the final descriptor to complete.
Once the last descriptor has executed, the channel is automatically disabled. This behavior ensures clean transaction termination without requiring explicit software shutdown.
Interrupts and Events
The DMAC can generate interrupts for block transfer completion, error detection and channel suspend conditions. These interrupts allow software to synchronize with hardware transfers while still minimizing CPU load.
In parallel, the DMAC can generate hardware events that trigger other peripherals or additional DMA channels, enabling fully autonomous data pipelines.
Benefits of SAM E51 DMAC Transfer Control
Proper use of DMAC transfer control delivers several key advantages. CPU utilization is significantly reduced because data movement no longer requires interrupt‑driven software loops. Power consumption is lowered as the CPU can remain in Sleep modes during transfers. Deterministic timing is improved because transfers occur in hardware with predictable arbitration. System robustness increases through built‑in error detection and recovery mechanisms.
Microchip Technology Solutions
Microchip Technology supports SAM E51 DMAC development with a comprehensive ecosystem. MPLAB® Harmony v3 provides DMAC peripheral libraries, descriptor management utilities and ready‑to‑run examples for ADC, USART, SPI and memory transfers. SAM D5x/E5x Family Data Sheet and application notes document advanced features such as FIFO thresholds, CRC usage and linked descriptors. Development boards like the SAM E51 Xplained series allow rapid prototyping and hands‑on learning.
Summary
Transfer control in the SAM E51 DMAC governs how data moves from trigger to completion. The process begins with a trigger, passes through arbitration and descriptor fetch, executes using flexible addressing and FIFO buffering, and concludes with interrupts or events. Write‑back descriptors ensure safe preemption, while error handling protects system integrity.
Understanding these mechanisms transforms DMA from a black box into a predictable and powerful tool. With this knowledge, you are prepared to design efficient, low‑power and highly autonomous data‑movement systems using the SAM E51 DMAC.