Understanding SAM E51 DMAC Units of Transfer

Last modified by Microchip on 2026/07/07 10:55

Introduction

Modern microcontrollers often spend a surprising amount of time moving data rather than processing it. Copying Analog‑to‑Digital Converter (ADC) samples to memory, feeding data to a Digital‑to‑Analog Converter (DAC), or streaming bytes through a serial interface can consume many Central Processing Unit (CPU) cycles if handled in software. The Direct Memory Access Controller (DMAC) in the SAM E51 microcontroller, provided by Microchip Technology, solves this problem by transferring data autonomously, allowing the CPU to focus on application logic.

This lesson introduces the units of transfer used by the SAM E51 DMAC. Understanding these units—beat, burst, block, and transaction—is essential before learning about descriptors, linked lists, and advanced Direct Memory Access (DMA) use cases.

The Role of the DMAC in SAM E51

The DMAC is a hardware engine that transfers data between peripherals and memory, or memory-to-memory, without CPU intervention. Transfers are initiated by triggers, which may come from peripherals (such as a USART receive event), software, or the event system.

Rather than thinking of DMA as one big copy, the DMAC organizes transfers hierarchically. Each level in this hierarchy has specific timing, interrupt, and atomicity characteristics. This structure allows precise control over performance, latency, and responsiveness.

Units of Transfer in the SAM E51 DMAC

The SAM E51 DMAC defines four nested units of transfer:

Beat → Burst → Block → Transaction

Each higher level is composed of one or more of the levels below it.

Beat: The Smallest Transfer Unit

SAME51 Direct Memory Access Controller (DMAC) Beat

A beat is the smallest possible data movement performed by the DMAC. It represents one DMA bus access.

In the SAM E51, the beat size is configured using the Block Transfer Control Register (BTCTRL), specifically the BEATSIZE field. The available sizes are:

8‑bit (byte)
16‑bit (half‑word)
32‑bit (word)

A beat transfer is atomic, meaning it cannot be interrupted by the CPU or by another DMA channel once it has started. This guarantees data integrity at the bus level.

Choosing the correct beat size is critical. For example, transferring a 16‑bit ADC result should use a 16‑bit beat to avoid misaligned accesses and unnecessary bus cycles.

Burst: A Group of Beats

SAME51 Direct Memory Access Controller (DMAC) Burst

A burst is a group of consecutive beat transfers performed back‑to‑back.

Like a beat, a burst transfer is atomic and cannot be interrupted. Arbitration between DMA channels occurs only between bursts, not during them.

The supported burst size depends on the processor family:

On Arm^® Cortex^®‑M0+–based devices, the burst size is always one beat, making burst and beat effectively identical.
On SAM E5x devices (including SAM E51), the burst size can be 1 to 16 beats, configured using the Channel Control A Register (CHCTRLA).

This capability allows the SAM E51 to achieve higher throughput by reducing arbitration overhead when transferring large, contiguous data sets.

Block: A Descriptor‑Defined Transfer

SAME51 Direct Memory Access Controller (DMAC) Block

A block is the amount of data transferred by one DMA descriptor. A block consists of 1 to 65,536 beats (1 to 64K beats).

Unlike beats and bursts, a block transfer can be interrupted. The DMAC may temporarily suspend a block if a higher‑priority DMA channel requests access, resuming later without data loss.

Blocks are the primary unit at which:

Interrupts are commonly generated
Events can be emitted
Source and destination addresses are updated

In practical terms, a block might represent:

A buffer of ADC samples
A packet of serial data
A waveform segment for a DAC

Transaction: A Complete DMA Operation

SAME51 Direct Memory Access Controller (DMAC) Transaction

A transaction is the complete transfer of all blocks in a DMA operation. A transaction may consist of:

A single block (using one descriptor), or
Multiple blocks linked together using linked descriptors

When multiple descriptors are linked, the DMAC automatically fetches the next descriptor when the current block completes. The transaction ends only when the final descriptor in the linked list has been processed.

Transactions define the highest‑level behavior of the DMAC, such as:

When a channel is disabled or suspended
When a transaction complete condition is reached

At this point, the DMAC can optionally generate an interrupt or event, depending on configuration.

Transition to Linked Descriptors

With the concept of a transaction defined, we now introduce linked descriptors. Linked descriptors allow the SAM E51 DMAC to perform complex, multi‑stage transfers without CPU involvement—for example, double buffering, circular buffers, or continuous streaming.

From this point forward, descriptor structure, linking, and memory layout become central topics, as they define how blocks are chained together into transactions.

Why These Transfer Units Matter

Understanding DMA transfer units provides several key benefits:

Higher CPU availability, since data movement occurs in hardware
Predictable timing, due to atomic beats and bursts
Scalable performance, using larger bursts and blocks on SAM E51
Cleaner software design, with fewer interrupt service routines
Lower power consumption, because the CPU can sleep while DMA runs

These advantages are especially important in data‑intensive applications such as motor control, signal processing, USB, and real‑time communications.

Summary

The SAM E51 DMAC organizes data movement into a clear hierarchy. A beat is a single bus transfer, grouped into bursts for efficiency. Bursts form blocks, which are defined by DMA descriptors and can be interrupted. One or more blocks together form a transaction, representing a complete DMA operation.

Mastering these concepts is essential for understanding DMA descriptors, linked lists, and advanced transfer modes. With this foundation, you are now prepared to explore how the SAM E51 uses descriptors to implement powerful, CPU‑independent data.